CDCU877 | CDCVF857 | CDC7005 | CDCM1804 | CDCP1803 | CDCF5801

CDCU877

• How fast can the CDCU877 operate yet maintain all specifications?
  • The device can maintain all specs up to 400MHz under nominal conditions and up to 340MHz under all conditions.


• What is the nominal condition of operation?
  • Vcc = 1.8V, Ambient Temp = 25°C, Nominal Silicon.


• How does one adjust the delay between the input and output clk signals? (3 different ways)
  • By attaching a capacitor from the Fbin pin to Gnd and from the nFbin pin to Gnd.
  • By attaching a capacitor differentially between the Fbin and nFbin pins.
  • By attaching a capacitive load at the output clk.


• How does one know what value of capacitor to attach to adjust the delay?
  • Increasing the capacitor value on Fbin or nFbin pin will advance the output clk edge with respect to the input clk and vice versa. Increasing the capacitor value at the output clk will delay the output clk with respect to the input clk. The input clk edge stays constant while only the output clk edge advances or delays.


• What is By-Pass mode?
  • In this mode, one turns the PLL off to operate the device as a pure buffer. Note, in this mode one will no longer be able to adjust the delay.


• How do I set the CDCU877 to operate in By-Pass mode?
  • Connect the AVdd pin to Gnd.


• Is the AC spec guarenteed in By-Pass mode?
  • Yes, except for the Static Phase Offset. All other specs such as skew and jitter will not change. The jitter performance is actually better since the PLL is turned off. However, the device will have a fixed (typically 2ns) propagation delay since this mode does not allow the delay to be adjusted to zero.

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CDCVF857

• Is the CDCVF857 compliant with JEDEC DDR1-400 A+ Spec?
  • Yes, it supports DDR1-400 A+ JEDEC spec defined for RDIMM using TSSOP based memory IC.


• What is the operation frequency range?
  • Frequency Range is 60MHz ~ 220MHz, and support all DDR1 nodes from DDR200 to DDR400 A+.


• What is the operation voltage?
  • Vdd = 2.3~2.7V for DDR200/266/333,
  • Vdd = 2.5~2.7V for DR400/400A+.


• What are available packages?
  • The CDCVF857 has two package options, TSSOP and QFN(MLF); BGA package is not available. Area of QFN package is smaller and thermal performance is better than BGA package, so QFN is recommended over BGA.


• How does one adjust the delay between the input and output clk signals?
  • By attaching a capacitor from the Fbin pin to Gnd and from the nFbin pin to Gnd.
  • By attaching a capacitor differentially between the Fbin and nFbin pins.
  • By attaching a capacitive load at the output clk.


• What is the improvement of the CDCVF857 over the CDCV857B?
  • The CDCVF857 increased Max frequency from 200MHz to 220MHz.
  • The CDCVF857 lowered Cycle to Cycle jitter from 50ps to 35ps.
  • The CDCVF857 lowered Period Jitter from 35ps to 30ps.
  • The CDCVF857 lowered Skew from 100ps to 40ps.

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CDC7005

• What is the reference clock signaling type and frequency range?
  • The reference clock frequency range is from 3.5MHz to 180 MHz. The specified signaling type is LVCMOS, which means a 0.4Vcc swing and Vdd/2 biasing is needed. However, we tested the part and found it typically works with a 600mV swing.


• What is the output frequency range?
  • The output frequency depends on the VCXO frequency, which is why the output freq range is not specified in the datasheet. The VCXO frequency range is from 10MHz to 800MHz. As long as the VCXO freq range is met, the device will function properly. For example, if the VCXO frequency is 10MHz and one chooses to divide by 16 on one of the outputs, then you will get a 625KHz frequency at the output.


• What is done if a single ended output is required?
  • If, for example, one needs an LVTTL clock, a signal converter, such as the SN65LVDS2. CDC7005 output provides around a 700mV swing and sometimes it can be used directly if the receiver can work with a 700mV swing (proper biasing may be required).


• If only one output is required from the differential pair, what is done with the remaining output?
  • As the Y0/Y0B is the LVPECL output, both need to be terminated properly whether one of them is used or not.


• What should be done with the unused outputs?
  • The unused outputs must be left open; otherwise they will draw currents unnecessarily.


• In active holdover mode, how long can the CDC7005 continue to provide the last known phase and frequency in the case of a missing reference clock?
  • The reference clock has to come back within 100 clock cycles and the filter circuitry must be designed carefully so that it has low leakage current.


• What is the jitter performance of the CDC7005?
  • No jitter value is specified in our datasheet because the jitter performance depends on the reference clock and VCXO noise performance, CDC7005 PLL and loop bandwidth optimization. In the case of identical reference clock and VCXO, different jitter data has been observed due to different loop bandwidth settings. Phase noise performance is provided in the datasheet based on a particular VCXO as an example. If a better performing VCXO is used, better results will be observed. As an example, the CDC7005 with a 622.08 MHz VCXO, was found as having well below 500fs of rms jitter (from 12kHz to 20MHz).


• How much jitter does the CDC7005 LVPECL path (buffer) add?
  • The CDC7005, as a buffer, adds less than 100fs rms jitter (12kHz to 20MHz).


• Are the five outputs independent from each other?
  • Yes, all outputs operate independently from each other. Each output can be programmed for divide down and enabled or disabled individually.


• Are the LVPECL outputs enabled after power-up?
  • Yes, all outputs are enabled after power-up to its default settings.


• What will the output skew be if the mode is, for example, 1-2-4-8-16, or any different mode not specified in the datasheet (page 15)?
  • The maximum output skew is 60ps, independant on the mode.


• Why is the loop bandwidth optimization critical for jitter cleaning?
  • Up to the loop bandwidth frequency, the output phase noise (jitter) follows the reference clock phase noise and after the loop bandwidth frequency, the output follows the VCXO phase noise. If the reference clock is cleaner than the VCXO at lower frequencies from the carrier, the higher loop bandwidth is desirable. If, on the other hand, the reference clock is noisier than VCXO, the lower loop bandwidth will help to clean jitter from the reference clock.


• How low can the CDC7005 loop bandwidth be set?
  • Sub 10Hz.


• How do I determine the loop bandwidth of the CDC7005?
  • TI has an Excel-based Loop Bandwidth Calculator downloadable from the CDC7005 product folder. By knowing the loop bandwidth parameters such as loop filter component values, PLL update frequency, charge pump current, and VCXO gain, the tool can be used to determine the loop bandwidth.


• How far can the device mutliply up or divide down by?
  • The device has two (one for the reference clock and another for feedback clock) internal 10 bit pre-dividers for the PFD (Phase Frequency Detector). Additionally, it has a post divider (values are 1,2,4,8,16) for the feedback path. For PLL operation, the reference clock and feedback clock frequency (PFD update frequency) must be the same. Thus, using the pre and post dividers, a wide number of multiplication (1.33x, 1.5x, 24x, 6.144x, etc.) and division factors (0.5x, 0.75x, 0.001x, etc.) are achievable.


• Lower frequency LVPECL VCXOs are very rare. Because of this can I use a single ended LVTTL VCXO?
  • Yes, you can use a LVTTL VCXO with proper divider and biasing circuitry. Biasing circuitry will help to fix the proper common mode voltage for the LVPECL input, which is necessary becuase the TTL swing is too high and needs to be reduced.


• Is it possible to use this device without SPI Interface?
  • Yes, the device has four internal registers and every bit of the register has been set to its default value. The device will operate at default mode after power up. At default mode, the reference clock frequency must be 1/8th that of the VCXO frequency.


• Why does the CDC7005 have an OPA integrated?
  • The OPA can be used as an active filter. An external OPA can also be used as an active filter.


• When should an OPA be used with the CDC7005?
  • An active filter should be used if the customer is not able to generate a high impedance Vctrl node with a passive filter. This can happen for example if the Vctrl input of the VCXO/VCSO/VCO is either leaky, bipolar, or badly designed. Therefore, between the CP_OUT and the OPA_IN, the CDC7005 can provide a high impedance node to overcome the limitation of an attached VCXO/VCSO/VCO. The best performance however, can be achieved with a passive filter.


• What is the noise floor of the PFD?
  • The phase noise floor of the PFD is around -170dBc/Hz at 240kHz from the carrier.


• How many transistors does the CDC7005 have?
  • 17300 transistors


• What process technology is used for the CDC7005?
  • RFSiGe


• What is the junction-to-case thermal resistance (Tjc)?
  • At low-k-board, it is 26.6°C/W.


• What is the Fit Rate and the MTBF?
  • The Fit Rate is 33.7 (failure is one thousand seconds) and MBTF is 2.96E+07 (device hours). This failure rate is based on qualification and/or reliability monitor data that is calculated at 0.7eV at 55°C with a 60% Upper Confidence Level.


• What is the maximum allowable junction temperature?
  • 125°C

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CDCM1804

• What is the maximum operating frequency for the CDCM1804?
  • 800MHz for the Y[0-2] LVPECL output and 200MHz for Y3 CMOS output. The device will work with higher frequency, but with reduced swing. *See graph in datasheet datasheet.


• What types of signals can the CDCM1804 accept?
  • The device has a very wide common-mode and hence can accept any signal with a 150mV differential swing. It can also accept any 3.3V or 2.5V single-ended signal.


• If one is using a single-ended signal type such as LVTTL or LVCMOS, what is required on the complementary input IN bar?
  • The unused IN bar can be tied to the VBB pin or needs to be biased to the common-mode point of the input signal through the external pull-up/pull-down.


• If only one of the two differential outputs is needed in an application, what needs to be done with the unused complementary output?
  • The unused output needs to be terminated through a 150 Ohm resistor to GND.


• What is the output skew between the LVPECL outputs Y[0-2]?
  • The output skew is typically 10ps.


• How much jitter does the CDCM1804 add to an input signal?
  • The CDCM1804 does not add any jitter to the signal, since it is not a PLL-based clock driver. The jitter should be 0.25ps rms max for LVPECL output and 0.4ps rms max for LVCMOS output.


• If, in an application, I only need one CMOS output and one LVPECL output, how should the device be configured?
  • All outputs Y[0-3] of the device can be turned off by grounding the individual VDD pins of each output. *See caution note on page 3 of datasheet.


• Because differential oscillators (TCXOs or VCXOs) are pretty expensive, can I use a cheaper LVTTL/LVCMOS oscillator to drive the CDCM1804?
  • Yes, as long as you bias the unused complementary output (see answer 3).


• What is the operating temperature of the CDCM1804?
  • The device supports industrial temperature which is -40 to 85°C.


• What divide ratios can the Y[0-3] outputs have?
  • The CDCM1804 has 18 divide modes which are listed in the datasheet.


• What is the process technology used for the CDCM1804?
  • RFSiGe


• What is the thermal resistance of the CDCM1804?
  • Please see the Package Thermal Specifications table in the device datasheet.


• What is the supply voltage supported by the CDCM1804?
  • Currently, the device supports a VCC range of 3.0V to 3.6V and will be charachterized for 2.5V operation in early 2004.


• What is the recommended termination for the CDCM1804?
  • See the application notes with the literature numbers of SCAA059 and SCAA062 for AC and DC coupling, respectively.


• Can I use the CDCM1804 to level translate between single-ended or differential signaling and still provide differential LVPECL and CMOS outputs?
  • Yes, the device can accept differential signals such as LVDS, LVPECL, CML, HSTL, SSTL-2 or LVCMOS/LVTTL all the while providing 3 LVPECL + 1 LVCMOS outputs.

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CDCP1803

• What types of signals can the CDCP1803 accept?
  • The device has a very wide common-mode and hence can accept any signal with a 150mV differential swing. It can also accept any 3.3V or 2.5V single-ended signal.


• If one is using a single-ended signal type such as LVTTL or LVCMOS, what is required on the complementary input IN bar?
  • The unused IN bar can be tied to the VBB pin or needs to be biased to the common-mode point of the input signal through the external pull-up/pull-down.


• If only one of the two differential outputs is needed in an application, what needs to be done with the unused complementary output?
  • The unused output needs to be terminated through a 150 Ohm resistor to GND.


• What is the output skew between the LVPECL outputs Y[0-2]?
  • The output skew is typically 10ps.


• How much jitter does the CDCP1803 add to an input signal?
  • The CDCP1803 does not add any jitter to the signal, since it is not a PLL-based clock driver. The jitter should be 0.25ps rms max.


• If, in an application, I only need one LVPECL output, how should the device be configured?
  • All outputs Y[0-2] of the device can be turned off by grounding the individual VDD pins of each output. *See caution note from page 3 of datasheet


• Because differential oscillators (TCXOs or VCXOs) are pretty expensive, can I use a cheaper LVTTL/LVCMOS oscillator to drive the CDCP1803?
  • Yes, as long as you bias the unused complementary output (see answer 3).


• What is the process technology used for the CDCP1803?
  • RFSiGe


• What is the thermal resistance of the CDCP1803?
  • Please see the Package Thermal Specifications table in the device datasheet .


• What is the recommended termination for the CDCP1803?
  • See the application notes with the literature numbers of SCAA059 and SCAA062 for AC and DC coupling, respectively.

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CDCF5801

• What is the reference clock signaling type and frequency range?
  • The reference clock frequency range is from 12.5 MHz to 240 MHz. The specified signaling type is LVCMOS, which means you need 0.4VDD swing and VDD/2 biasing. However, the device will work properly with only a 500 mV swing so that an LVPECL signal (one of the differential pairs) can drive the CDCF5801.


• What is the output frequency range and signaling level?
  • The output frequency range is from 25 MHz to 280 MHz. Because the CDCF5801 has a differential, but not a true differential, output, it can be configured as an LVPECL, LVDS, or HSTL signal with the use of divider and biasing resistors. Both outputs can also be configured as an LVTTL signal, where one output will be complementary to the other.


• If one single ended output is required what does one do with the other output?
  • The unused output (such as CLKB) can be left open.


• If one wants to use the CDCF5801 as a simple multiplier, what should one do with LEADLAG and DLYCTRL pins?
  • The LEADLAG and DLYCTRL pins must be connected to either GND or VCC.


• It looks like the device does NOT have a feedback pin; can one use the CDCF5801 as a zero delay multiplier?
  • Yes, the CDCF5801 can be used as a zero delay multiplier. In order to make the loop complete, the input CLK has to be connected to the LEADLAG pin or the REFCLK has to be connected to DLYCTRL pin.


• Is there any restriction on which clock frequency can be connected to the DLYCTRL or LEADLAG pin?
  • The frequency of the DLYCTRL pin must be equal to or less than the frequency of the LEADLAG pin.


• What are the LEADLAG and DLYCTRL pins?
  • These two pins are the inputs of a phase aligner.


• How do the LEADLAG and DLYCTRL pins work?
  • These are the simple input pins of the phase aligner. The phase aligner always compares the phases of two signals and determines whether the output clock (CLK/CLKB) will advance or delay depending upon the phase position of the LEADLAG pin signal with respect to the DLYCTRL pin signal. If, for example, the LEADLAG signal is leading with respect to the DLYCTRL signal (which means the LEADLAG pin position will be considered HIGH), then the output clock (CLK/CLKB) will be advanced. With every rising edge of the DLYCTRL signal, the clock output will be advanced (if LEADLAG is HIGH) or delayed (if LEADLAG is LOW) by one step, which is 1/384 of the CLKOUT period or 2.6 mUI. So the output phase will be delayed or advanced with respect to its previous phase position.


• If there is no signal at the DLYCTRL pin, what will happen?
  • If there is no signal at DLYCTRL (means no rising edge), the phase of output clock (CLKOUT) will be unchanged with respect to the input clock phase, independent of the LEADLAG pin signaling level.


• What is the phase relation of the input and output of the CDCF5801 after power up?
  • The phase relation between the input and output clocks after power up is unknown.


• What will happen if there is a continuous signal at the DLYCTRL pin and the LEADLAG pin is either HIGH or LOW?
  • The output clock phase will be continuously advancing or delaying.


• What is the impact on the output phase by the frequency of the DLYCTRL pin?
  • The higher the frequency, the quicker the updates.


• How does one advance or delay the output clock phase with respect to its previous position for a fixed time, such as 1 ns or 90°?
  • Using a simple micro-controller, like the TI MSP430, one can generate required clock cycles for the DLYCTRL pin and either a HIGH or LOW signal for the LEADLAG pin.


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