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TMS320C6455


Power Requirements | Reference Designs | Resources | Related Links to SBDs


Power Requirements for TMS320C6455
  Pin Name Voltage (V) Imax (mA) Tolerance Sequencing Order Timing Delay
Core CVDD 1.25 3000 ±3% 2 DVDD33 supply must be stable 0.5-200ms before CVDD supply is stable.
Digital I/O DVDD33 3.3 175 ±5% 1
Analog I/O PLLV1, PLLV2, AVDLL1, AVDLL2 1.8 75 ±5% 3 Supplies must be stable 200ms after CVDD supply is stable.
Digital I/O DVDD18, DVDDR 1.8 70 ±5%
Digital I/O DVDD15 1.8/1.05 66 ±5%
Digital I/O DVDDRM, DVDD12 1.25 275 ±3%
Analog I/O AVDDT, AVDDA 1.25 275 ±5%

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Reference Designs for TMS320C6455
Name File Name/Size Date Download
5V Input
5 Vin solution for (6) C6455 DSP’s providing 15 A/1.2 V total Core Supply slvr304.pdf, 121KB Feb 2006
5Vin Power Design using Integrated-FET DCDC Converters and LDO's slvr326.pdf, 1.11 MB Mar 2008
12V Input
12Vin Power Design using Integrated-FET DCDC Converters and LDO's slvr327.pdf, 1.11 MB Mar 2008

Note: Unless otherwise noted, these reference designs are tested to meet the specs given in the above power specification table.

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Resources for TMS320C6455

Related System Block Diagrams (SBDs)

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