TI Home > Power Management > TMS320DM355

Power Management

Cross Reference

Application Notes

Training

Tools & Software

Block Diagrams

Reference Designs

Analog eLAB ™

TMS320DM355


Power Requirements | Reference Designs | Related Links to SBDs


Power Requirements for TMS320DM355
  Pin Name Voltage (V) Imax (mA) Tolerance Sequencing Order Timing Delay
Vcore CVdd, Vdda_pll1, Vdda_pll2, Vddd13_usb, Vdda13_usb 1.3 210 ±5% 1  
I/O Vdd_ddr, Vdda18_dac 1.8 30 ±5% 2 1.8V and 3.3V can also be powered on simultaneously.
I/O Vdd, Vdda33_ddrdll, Vdda33_usb, Vdda33_usb_pll, Vdd_vin, Vdd_vout 3.3 95 ±5% 3

*Note: Sequencing (Power-up): 1.8V & 3.3V remain low until 1.3V rail reaches 0.9V. At this time, the 1.8V and 3.3V can ramp at the same time. RESET: ≥ 5ms

Back to Top of Page



Reference Designs for TMS320DM355
Name File Name/Size Date Download
3.3 / 5V Input
2.0V – 5.5V Wide Vin, High Efficiency Discrete Power Solution for the DM355 slva288.pdf, 186 KB 01 Nov 2007
5Vin DM355 Power using a Multiple-Output DCDC Converter with Integrated FETs slvr330.pdf, 295 KB 26 Mar 2008
5Vin DM355 Power using LDO's slvr331.pdf, 379 KB 26 Mar 2008

Note: Unless otherwise noted, these reference designs are tested to meet the specs given in the above power specification table.

Back to Top of Page

Related System Block Diagrams (SBDs)

Back to Top of Page

 


Selection & Solution Guides   

  • Power Management Selection Guide (Rev. H) (slvt145h.pdf, 4.83 MB)
    11 Apr 2008 Download
  • LED Reference Design Cookbook (slyt349.pdf, 2.77 MB)
    Download
  • Battery Charger Catalog 3Q 2008 (slym069.pdf, 1.87 MB)
    Download