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TMS320C642x

Power Requirements | Reference Designs | Resources

Power Requirements for TMS320C642x
Core, I/O Pin Name Voltage (V) Imax (mA) Tolerance Sequencing Order Timing Delay
Core CVDD 1.2* 1480 ±5% 3 All supplies must be stable within 200ms after power ramp begins.
I/O DVDD33 3.3 40 ±5% 1
I/O DVDDR2, DDR_VDDDLL, PLLVPRW18, MXVDD 1.8 140 ±5% 2

* Note:

  • CVDD of 1.2V can be used for devices ending in -7/-6/-5/-4/-Q6/-Q5/-Q4 devices. CVDD of 1.05 can be used for devices ending in -7/-6/-5/-4/-L/-Q5.
  • It is recommended to use an EMI filter at the input of the PLLPWR18 pin. See the C642x datasheet for more details.

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Reference Designs for TMS320C642x
Name File Name/Size Date Download
5V Input
5Vin C642x Power using DC/DC Controllers and LDO slta059, 742 KB Oct 2008
5Vin C642x Power using Integrated-FET DC/DC Converters and LDO slta061, 550 KB Oct 2008
5Vin C642x Power using a PMIC (Multi-output DC/DC Converter) slta062, 302 KB Oct 2008
12V Input
12Vin C642x Power using Integrated-FET DC/DC Converters and LDO slta060, 310 KB Oct 2008

Note: Unless otherwise noted, these reference designs are tested to meet the specs given in the above power specification table.

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Resources for TMS320C642x

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Selection & Solution Guides   

  • Power Management Selection Guide (Rev. H) (slvt145h.pdf, 4.83 MB)
    11 Apr 2008 Download
  • LED Reference Design Cookbook (slyt349.pdf, 2.77 MB)
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  • Battery Charger Catalog 3Q 2008 (slym069.pdf, 1.87 MB)
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