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Block Diagrams

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Part Number   Status  
Sub Family   		Output Level   VCC (V)   Output Frequency (min) (Mhz)   Output Frequency (max) (Mhz)   Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)   Output Skew (ps)   Divider Ratio   Multiplier Ratio   No. of 100/133 MHz Outputs   Operating Temp Range (Celsius)   Rating   Priority (type 2)   Input Level   No. of Outputs   IO Supply (Volts)   Pin/Package   Approx. Price (US$)  
Description  
  Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending   Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending
CDCE906 ACTIVE NON-VCXO INPUT LVCMOS 3.3 0 167 60ps 150 Universal Ratio Universal Ratio 6 0 to 70 Catalog 1 Crystal, LVCMOS, Differential 20TSSOP 2.2 Programmable 3-PLL Clock Synthesizer / Multiplier / Divider
CDCE949 ACTIVE VCXO INPUT LVCMOS 1.8,3.3 230 60 ps 150 Universal Ratio Universal Ratio -40 to 85 Catalog 1 Crystal, LVCMOS 9 2.5 to 3.3 24TSSOP 2.35 Programmable 4-PLL VCXO Clock Synthesizer with 2.5V or 3.3V LVCMOS Outputs
CDCM7005 ACTIVE EXTERNAL VCXO OUTPUT LVPECL,LVCMOS 3.3 1500 1,2,3,4,6,8,16 -40 to 85 Catalog 1 LVCMOS (REF_CLK),LVPECL (VCXO_CLK) 5 48VQFN ,  64BGA 9.5 High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO