TI Home > Applications > DLP® Front Projection System > Block Diagrams

Block Diagrams

2 Results - Use Parametric Search to refine these results.



Results Table Legend
 
Suggested Devices

1 - 2 of 2 Results Page  1 |    

Part Number   Status  
Sub Family   		No. of 100/133 MHz Outputs   Input Level   Output Level   VCC (V)   Output Frequency (min) (Mhz)   Output Frequency (max) (Mhz)   Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)   Output Skew (ps)   Multiplier Ratio   Operating Frequency Range (min) (MHz)   Operating Temp Range (Celsius)   Rating   Priority (type 2)   Operating Frequency Range (max) (MHz)   Pin/Package   Approx. Price (US$)  
Description  
  Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending   Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending Sort Ascending Sort Descending
CDCD5704 ACTIVE RAMBUS/XDR 4 HCLK XDR, RSL 2.5 300 667 40 ps 15 3, 4, 5, 6, 8, 4.5, 7.5, 3.75 100 0 to 70 Catalog 1 133 28TSSOP 2.95 Rambus XDR(TM) Clock Generator
CDCDLP223 ACTIVE NON-VCXO INPUT 1 Crystal LVTTL, HCLK 3.3 20 400 75 ps 1, 5, 15 -40 to 85 Catalog 1 20TSSOP 2.9 3.3V Clock Synthesizer for DLP Systems