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74SSTUB32868 Status: ACTIVE

28-Bit to 56-Bit Registered Buffer with Address-Parity Test


      
         
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 74SSTUB32868
Frequency(Max)(MHz)410  
VCC(V)1.8  
Input LevelSSTL_18  
No. of Outputs56  
Output Drive(mA)8  
Vcc range(V)1.7 to 1.9  
Output LevelSSTL_18  
Pin/Package176NFBGA  
Static Current(mA)50  
Approx. Price (US$) 6.15 | 1ku  
 Samples
 Inventory

Customers Who Evaluated This Product Also Evaluated

  • 74SSTUB32868A: 28-Bit to 56-Bit Registered Buffer with Address-Parity Test
  • CDCUA877: 1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications

Product Information

Features

  • Member of the Texas Instruments Widebus+™ Family
  • Pinout Optimizes DDR2 DIMM PCB Layout
  • 1-to-2 Outputs Supports Stacked DDR2 DIMMs
  • One Device Per DIMM Required
  • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
  • Supports SSTL_18 Data Inputs
  • Differential Clock (CLK and CLK) Inputs
  • Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable, Control, and RESET Inputs
  • Checks Parity on DIMM-Independent Data Inputs
  • Supports Industrial Temperature Range (-40°C to 85°C)
  • RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except QERR
  • APPLICATIONS
    • DDR2 registered DIMM

Widebus+ is a trademark of Texas Instruments.

Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads.

All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.

The 74SSTUB32868 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

The 74SSTUB32868 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low).

View All Description in Datasheet

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierSymbolsFootprintsSamples
74SSTUB32868ZRHRACTIVE-40 to 856.15 | 1kuNFBGA (ZRH) | 176 View 1000 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this FootprintContact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:19 PM GMT, 22 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 12 Weeks74SSTUB32868ZRHR
AmericasArrow >1k
Avnet >1k
Newark 1k
AsiaFarnell Asia 1k
WPI 1k
WorldwideDigiKey 863
Mouser Electronics 1k
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
74SSTUB32868ZRHR RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for 74SSTUB32868 Help

Datasheet

Application Notes

View Application Notes for DDR2 Register

Simulation Models

Customers Who Evaluated This Product Also Evaluated...
Part # Name Product Family Comments
74SSTUB32868A 28-Bit to 56-Bit Registered Buffer with Address-Parity Test MEMORY INTERFACE CLOCKS AND REGISTERS-DDR2 REGISTER TI customers also evaluated this product.
CDCUA877 1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 0 DELAY PLL-DIFFERENTIAL ENDED TI customers also evaluated this product.

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