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ADS62P22: Dual 12-bit 65MSPS ADC with selectable DDR LVDS or CMOS outputs
Product Information
Features
Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
Simultaneous Sample and Hold
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
Serialized LVDS Outputs with Programmable Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp
Internal Reference with External Reference Support
No External Decoupling Required for References
3.3-V Analog and Digital Supply
48 QFN Package (7 mm × 7 mm)
Pin Compatible 14-Bit Family (ADS624X - SLAS542)
Feature Compatible Quad Channel Family (ADS644X - SLAS531 and ADS642X - SLAS532)
APPLICATIONS
Base-Station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
Description
ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design.
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Inventory
Reported Distributor Inventory as of 12:19 PM GMT, 20 Nov 2009
** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.
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