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CD4006B Status: OBSOLETE

CMOS 18-Stage Static Shift Register

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Datasheet

Download - PDF Icon
  • CMOS 18-Stage Static Shift Register (cd4006b.pdf, 381 KB)
    19 Nov 1998 Download

Other qualified versions of CD4006B

Version Part Number Definition
Military CD4006B-MIL QML certified for Military and Defense Applications

Product Information

Features

  • Fully static operation
  • Shifting rates up to 12 MHz @ 10 V (typ.)
  • Permanent register storage with clock line high or low - no information recirculation required
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' series CMOS Devices"
  • Applications
    • Serial shift registers
    • Frequency division
    • Time delay circuits

Description

CD4006B types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path.

A common clock signal is used for all stages. Data are shifted to the next stage on negative-going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8, and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 stages can be implemented using one CD4006B package. Longer shift register sections can be assembled by using more than one CD4006B.

To facilitate cascading stages when clock rise and fall times are slow, an optional output (D1+4') that is delayed one-half clock-cycle, is provided (see Truth Table for Output from Term. 2).

The CD4006B types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

    

Pricing / Packaging / CAD Design Tools / Samples

PackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Package | PinsTop Side MarkingFootprintsSamples
CD4006BEOBSOLETE-55 to 125PDIP (N) | 14 View Download CAD Format for this FootprintNot Available

Quality & Lead (Pb)-Free Data

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Technical Documents

Datasheets

  • CMOS 18-Stage Static Shift Register (cd4006b.pdf, 381 KB)
    19 Nov 1998 Download

Application Notes

  • Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm, 8 KB)
    24 May 2004 Abstract
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (szza036b.htm, 8 KB)
    28 May 2003 Abstract
  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics (scha004.htm, 9 KB)
    03 Dec 2001 Abstract

View Application Notes for Shift Registers

User Guides

  • LOGIC Pocket Data Book (Rev. B) (scyd013b.pdf, 6001 KB)
    16 Jan 2007 Download
  • Signal Switch Data Book (Rev. A) (scdd003a.pdf, 18396 KB)
    14 Nov 2003 Download

More Literature

  • Logic Selection Guide 2007 (Rev. Z) (sdyu001z.pdf, 2862 KB)
    24 Apr 2007 Download
  • Military Semiconductors Selection Guide 2004-2005 (Rev. D) (sgyc003d.pdf, 964 KB)
    10 Aug 2004 Download
  • Logic Cross-Reference (Rev. A) (scyb017a.pdf, 2938 KB)
    07 Oct 2003 Download

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