Flip-Flops, Latches and Registers - D-Type Flip-Flops - CD74AC74

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Datasheet

CD54AC74, CD74AC74 (Rev. D) (PDF 531 KB)
05 Dec 2002

	CD54AC74	CD74AC74
Voltage Nodes(V)	5, 3.3
Technology Family	AC	AC
Rating	Military	Catalog
	Samples	Samples
	Inventory	Inventory

Other qualified versions of CD74AC74

Version	Part Number	Definition
Military	CD54AC74	QML certified for Military and Defense Applications

Customers Who Evaluated This Product Also Evaluated

SN74AC74: Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

Product Information

Features

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

Description

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
CD74AC74E	ACTIVE	-55 to 125	0.33 \| 1ku	PDIP (N) \| 14	View	25 \| TUBE	Purchase Samples
CD74AC74EE4	ACTIVE	-55 to 125	0.33 \| 1ku	PDIP (N) \| 14	View	25 \| TUBE	Purchase Samples
CD74AC74M	ACTIVE	-55 to 125	0.33 \| 1ku	SOIC (D) \| 14	View	50 \| TUBE	Purchase Samples
CD74AC74M96	ACTIVE	-55 to 125	0.31 \| 1ku	SOIC (D) \| 14	View	2500 \| LARGE T&R	Contact TI Distributor or Sales Office
CD74AC74M96E4	ACTIVE	-55 to 125	0.31 \| 1ku	SOIC (D) \| 14	View	2500 \| LARGE T&R	Contact TI Distributor or Sales Office
CD74AC74M96G4	ACTIVE	-55 to 125	0.31 \| 1ku	SOIC (D) \| 14	View	2500 \| LARGE T&R	Contact TI Distributor or Sales Office
CD74AC74ME4	ACTIVE	-55 to 125	0.33 \| 1ku	SOIC (D) \| 14	View	50 \| TUBE	Purchase Samples
CD74AC74MG4	ACTIVE	-55 to 125	0.33 \| 1ku	SOIC (D) \| 14	View	50 \| TUBE	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:08 PM GMT, 25 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 20 WeeksCD74AC74E
Americas	Avnet	>1k
Americas	Rochester Electronics	>1k
Asia	Farnell Asia	675
Europe	Avnet-SILICA	900
	Compel	654
	EBV Elektronik	125
	Farnell	512
Worldwide	Mouser Electronics	584
TI Lead Time*: 20 WeeksCD74AC74EE4
None Reported View Distributors
TI Lead Time*: 20 WeeksCD74AC74M
Americas	Arrow	>1k
	Avnet	>1k
	Newark	>1k
	Rochester Electronics	>1k
Asia	Farnell Asia	172
Europe	Arrow Northern Europe	254
	Avnet-SILICA	>1k
	EBV Elektronik	>1k
	Farnell	66
Worldwide	DigiKey	726
Worldwide	Mouser Electronics	845
TI Lead Time*: 20 WeeksCD74AC74M96
Americas	Rochester Electronics	>1k
Europe	EBV Elektronik	215
Worldwide	DigiKey	689
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 20 WeeksCD74AC74M96E4
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksCD74AC74M96G4
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksCD74AC74ME4
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksCD74AC74MG4
Worldwide	DigiKey	Available
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CD74AC74E	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	View	View
CD74AC74EE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	View	View
CD74AC74M	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74AC74M96	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74AC74M96E4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74AC74M96G4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74AC74ME4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74AC74MG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for CD74AC74

Datasheet

CD54AC74, CD74AC74 (Rev. D) (PDF, 531 KB)
05 Dec 2002

Application Notes

Input and Output Characteristics of Digital Integrated Circuits (HTM, 9 KB) 9405 views
01 Oct 1996 Read Abstract
Live Insertion (HTM, 8 KB) 2444 views
01 Oct 1996 Read Abstract
TI IBIS File Creation, Validation, and Distribution Processes (HTM, 9 KB) 3906 views
29 Aug 2002 Read Abstract
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 27271 views
24 May 2004 Read Abstract
Designing With Logic (Rev. C) (HTM, 8 KB) 9164 views
01 Jun 1997 Read Abstract
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (HTM, 8 KB) 2081 views
01 Apr 1996 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 21719 views
28 May 2003 Read Abstract
Implications of Slow or Floating CMOS Inputs (Rev. C) (HTM, 8 KB) 7120 views
01 Feb 1998 Read Abstract
CMOS Power Consumption and CPD Calculation (Rev. B) (HTM, 9 KB) 3173 views
01 Jun 1997 Read Abstract

View Application Notes for D-Type Flip-Flops

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 47392 views
16 Jan 2007

Selection Guides

Logic Guide 2009 (Rev. Z) (PDF, 4263 KB) 90790 views
23 Jul 2009

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 15434 views
07 Oct 2003
HiRel Unitrode Power Management Brochure (PDF, 206 KB) 660 views
07 Jul 2009

Customers Who Evaluated This Product Also Evaluated...
Part #	Name	Product Family	Comments
SN74AC74	Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset	FLIP-FLOPS, LATCHES AND REGISTERS-D-TYPE FLIP-FLOPS	TI customers also evaluated this product.

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CD74AC74 Status: ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

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Datasheet

Other qualified versions of CD74AC74

Customers Who Evaluated This Product Also Evaluated

Product Information

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Description

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

More Literature

Support and Community

Customer Tags

Other Support

CD74AC74 Status: ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

Most Popular Links

Datasheet

Other qualified versions of CD74AC74

Customers Who Evaluated This Product Also Evaluated

Product Information

Features

Description

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

More Literature

Related Products

Support and Community

Customer Tags

Other Support