Flip-Flops, Latches and Registers - D-Type Flip-Flops - CD74ACT74-Q1

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Datasheet

Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. A) (PDF 189 KB)
29 Jan 2008

	CD74ACT74-Q1
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Input Level	TTL
Output Level	CMOS
Output Drive(mA)	-24/24
No. of Bits	2
No. of Outputs	4
Static Current	0.004
th(ns)	0
tpd max(ns)	9.5
tsu(ns)	4
Technology Family	ACT
Rating	Automotive
	Samples
	Inventory

Other qualified versions of CD74ACT74-Q1

Version	Part Number	Definition
Catalog	CD74ACT74	TI's standard catalog product
Military	CD54ACT74	QML certified for Military and Defense Applications

Product Information

Features

Qualified for Automotive Applications
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design

Description

The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
CD74ACT74QM96G4Q1	ACTIVE	-40 to 125	0.36 \| 1ku	SOIC (D) \| 14	View	2500		Purchase Samples
CD74ACT74QM96Q1	ACTIVE	-40 to 125	0.36 \| 1ku	SOIC (D) \| 14	View	2500	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:09 PM GMT, 26 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 20 WeeksCD74ACT74QM96G4Q1
None Reported View Distributors
TI Lead Time*: 20 WeeksCD74ACT74QM96Q1
None Reported View Distributors
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CD74ACT74QM96G4Q1	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CD74ACT74QM96Q1	Pb-Free (RoHS)	CU NIPDAU	Level-2-250C-1 YEAR/Level-1-235C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for CD74ACT74-Q1

Datasheet

Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. A) (PDF, 189 KB)
29 Jan 2008

Application Notes

TI IBIS File Creation, Validation, and Distribution Processes (HTM, 9 KB) 3911 views
29 Aug 2002 Read Abstract
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 27294 views
24 May 2004 Read Abstract
Selecting the Right Level Translation Solution (Rev. A) (HTM, 8 KB) 15623 views
22 Jun 2004 Read Abstract
Designing With Logic (Rev. C) (HTM, 8 KB) 9174 views
01 Jun 1997 Read Abstract
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (HTM, 8 KB) 2082 views
01 Apr 1996 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 21746 views
28 May 2003 Read Abstract
Implications of Slow or Floating CMOS Inputs (Rev. C) (HTM, 8 KB) 7134 views
01 Feb 1998 Read Abstract
CMOS Power Consumption and CPD Calculation (Rev. B) (HTM, 9 KB) 3175 views
01 Jun 1997 Read Abstract

View Application Notes for D-Type Flip-Flops

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 47453 views
16 Jan 2007

Selection Guides

Logic Guide 2009 (Rev. Z) (PDF, 4263 KB) 90936 views
23 Jul 2009

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 15456 views
07 Oct 2003

CD74ACT74-Q1 Status: ACTIVE

Automotive Catalog Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

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Datasheet

Other qualified versions of CD74ACT74-Q1

Product Information

Features

Description

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

More Literature

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