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CD74HCT297 Status: ACTIVE

High Speed CMOS Logic Digital Phase-Locked-Loop

      Harris
         
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Datasheet

Download - PDF Icon
  • CD54/74HC297, CD74HCT297 (Rev. B) (cd74hct297.pdf, 246 KB)
    16 Apr 2003 Download

 CD74HCT297
Voltage Nodes(V)5  
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Technology FamilyHCT  
 Samples
 Inventory

Customers Who Evaluated This Product Also Evaluated

  • CD74HCT4046A: High Speed CMOS Logic Phase-Locked-Loop with VCO
  • CD74HC7046A: High Speed CMOS Logic Phase-Locked Loop with VCO and Lock Detector
  • CD74HC297: High Speed CMOS Logic Digital Phase-Locked-Loop

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Product Information

Features

  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher Order Loops
  • Useful Frequency Range
    • K-Clock...DC to 55MHz (Typ)
    • I/D-Clock...DC to 35MHz (Typ)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard...XORPDOUT, ECPDOUT
    • Bus Driver...I/DOUT
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • ’HC297 Types
    • Operation Voltage...2 to 6V
    • High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
  • CD74HCT297 Types
    • Operation Voltage...4.5 to 5.5V
    • Direct LSTTL Input Logic Compatibility VIL =0.8V (Max), VIH =2V (Min)
    • CMOS Input Compatibility II 1µA at VOL , VOH

Data sheet acquired from Harris Semiconductor

Description

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierFootprintsSamples
CD74HCT297EACTIVE-55 to 1252.20 | 1kuPDIP (N) | 16 View 25 | TUBE Download CAD Format for this FootprintPurchase Samples
CD74HCT297EE4ACTIVE-55 to 1252.20 | 1kuPDIP (N) | 16 View 25 | TUBE Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
CD74HCT297EAs of 10:06 AM GMT, 04 Dec 2008As of 10:06 AM GMT, 04 Dec 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* 2225 | 17 Dec 4 Weeks AmericasMouser Electronics 37
 >10k | 7 Jan Rochester Electronics >1k
  EuropeEBV Elektronik 75
CD74HCT297EE4As of 10:06 AM GMT, 04 Dec 2008As of 10:06 AM GMT, 04 Dec 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* 2225 | 17 Dec 4 Weeks None Reported
View Distributors		   
 >10k | 7 Jan     
View all Distributors  

* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
CD74HCT297E RoHS Compliant Pb-Free (RoHS) CU NIPDAU N/A for Pkg TypeViewView
CD74HCT297EE4 RoHS Compliant Pb-Free (RoHS) CU NIPDAU N/A for Pkg TypeViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Datasheets

  • CD54/74HC297, CD74HCT297 (Rev. B) (cd74hct297.pdf, 246 KB)
    16 Apr 2003 Download

Application Notes

  • Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm, 8 KB)
    24 May 2004 Abstract
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (szza036b.htm, 8 KB)
    28 May 2003 Abstract
  • TI IBIS File Creation, Validation, and Distribution Processes (szza034.htm, 9 KB)
    29 Aug 2002 Abstract
  • Implications of Slow or Floating CMOS Inputs (Rev. C) (scba004c.htm, 8 KB)
    01 Feb 1998 Abstract
  • CMOS Power Consumption and CPD Calculation (Rev. B) (scaa035b.htm, 9 KB)
    01 Jun 1997 Abstract
  • Designing With Logic (Rev. C) (sdya009c.htm, 8 KB)
    01 Jun 1997 Abstract
  • SN54/74HCT CMOS Logic Family Applications and Restrictions (scla011.htm, 8 KB)
    01 May 1996 Abstract
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (scla008.htm, 8 KB)
    01 Apr 1996 Abstract

View Application Notes for Phase-Locked-Loops (PLLs) and Oscillators

User Guides

  • LOGIC Pocket Data Book (Rev. B) (scyd013b.pdf, 6001 KB)
    16 Jan 2007 Download
  • Signal Switch Data Book (Rev. A) (scdd003a.pdf, 18396 KB)
    14 Nov 2003 Download

More Literature

  • Logic Selection Guide 2007 (Rev. Z) (sdyu001z.pdf, 2862 KB)
    24 Apr 2007 Download
  • Logic Cross-Reference (Rev. A) (scyb017a.pdf, 2938 KB)
    07 Oct 2003 Download
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