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CDC5801A Status: ACTIVE

Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignment


      
         
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 CDC5801A
VCC(V)3.3  
Input LevelLVCMOS, LVTTL  
Output LevelLVDS, LVPECL, LVTTL  
Pin/Package24SSOP/QSOP  
Temp Range(C)S(-40 to 85)  
Output Frequency(Min)(Mhz)150  
Output Frequency(Max)(Mhz)500  
Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)P-P PA bypassed=40ps, PA active=70ps, Division mode=75ps  
Divider Ratio2, 3, 4  
Multiplier Ratio4, 6, 8  
Operating Temp Range(Celsius)-40 to 85  
 Samples
 Inventory

Customers Who Evaluated This Product Also Evaluated

  • CDCF5801A: Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps
  • CDCE62002: Four Output Clock Generator/Jitter Cleaner with Integrated Dual VCOs
  • CDCM61001: 1:1 Ultra Low Jitter Crystal-In Clock Generator
  • CDCE62005: 5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO

Product Information

Features

  • Low Jitter Clock Multiplier by x4, x6, x8. Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz
  • Fail-Safe Power Up Initialization
  • Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz
  • 2.6 mUI Programmable Bidirectional Delay Steps
  • Typical 8-ps Phase Jitter (12 kHz to 20 MHz) at 500 MHz
  • Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) at 500 MHz
  • One Single-Ended Input and One Differential Output Pair
  • Output Can Drive LVPECL, LVDS, and LVTTL
  • Three Power Operating Modes to Minimize Power
  • Low Power Consumption (Typical 200 mW at 500 MHz)
  • Packaged in a Shrink Small-Outline Package (DBQ)
  • No External Components Required for PLL
  • Spread Spectrum Clock Tracking Ability to Reduce EMI
  • Applications: Video Graphics, Gaming Products, Datacom, Telecom
  • Accepts LVCMOS, LVTTL Inputs for REFCLK Terminal
  • Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF = 1.6 V)
  • Supports Industrial Temperature Range of -40°C to 85°C

Description

The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.

The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals.

The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.

View All Description in Datasheet

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierSymbolsFootprintsSamples
CDC5801ADBQACTIVE-40 to 854.10 | 1kuSSOP/QSOP (DBQ) | 24 View 50 | TUBE Download CAD Format for this Symbol Download CAD Format for this Footprint
CDC5801ADBQG4ACTIVE-40 to 854.10 | 1kuSSOP/QSOP (DBQ) | 24 View 50 | TUBE Download CAD Format for this Symbol Download CAD Format for this Footprint
CDC5801ADBQRACTIVE-40 to 853.70 | 1kuSSOP/QSOP (DBQ) | 24 View 2500 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
CDC5801ADBQRG4ACTIVE-40 to 853.70 | 1kuSSOP/QSOP (DBQ) | 24 View 2500 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:01 PM GMT, 22 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 20 WeeksCDC5801ADBQ
AmericasAvnet 30
AsiaWPI 44
EuropeAvnet-SILICA 90
WorldwideDigiKey 123
TI Lead Time*: 20 WeeksCDC5801ADBQG4
WorldwideDigiKey  Available
TI Lead Time*: 20 WeeksCDC5801ADBQR
WorldwideDigiKey  Available
TI Lead Time*: 20 WeeksCDC5801ADBQRG4
WorldwideDigiKey  Available
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
CDC5801ADBQ RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEARViewView
CDC5801ADBQG4 RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEARViewView
CDC5801ADBQR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEARViewView
CDC5801ADBQRG4 RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEARViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for CDC5801A Help

Datasheet

Simulation Models

Customers Who Evaluated This Product Also Evaluated...
Part # Name Product Family Comments
CDCF5801A Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps PLL BUFFERS-PHASE ALIGNER TI customers also evaluated this product.
CDCE62002 Four Output Clock Generator/Jitter Cleaner with Integrated Dual VCOs ULTRA LOW JITTER SYNTHESIZER AND JITTER CLEANER-INTERNAL VCO OUTPUT TI customers also evaluated this product.
CDCM61001 1:1 Ultra Low Jitter Crystal-In Clock Generator ULTRA LOW JITTER SYNTHESIZER AND JITTER CLEANER-INTERNAL VCO OUTPUT TI customers also evaluated this product.
CDCE62005 5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO ULTRA LOW JITTER SYNTHESIZER AND JITTER CLEANER-INTERNAL VCO OUTPUT TI customers also evaluated this product.
CDCE72010 10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner WIRELESS BASE STATION CLOCKS-TRX ADC/DAC FREQUENCY SYNTHERSIZER/JITTER CLEANERS TI customers also evaluated this product.
CDCM61004 1:4 Ultra Low Jitter Crystal-In Clock Generator ULTRA LOW JITTER SYNTHESIZER AND JITTER CLEANER-INTERNAL VCO OUTPUT TI customers also evaluated this product.
CDCVF25084 3.3V x4 Clock Multiplier With 8 Outputs PLL BUFFERS-Multiplier / Divider TI customers also evaluated this product.
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CDCM7005 High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO ULTRA LOW JITTER SYNTHESIZER AND JITTER CLEANER-EXTERNAL VCXO OUTPUT TI customers also evaluated this product.

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