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CDCE62005 Status: ACTIVE

5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO


      
         
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Special Note

Pre-programming of customer-specific settings is available. Contact your local Texas Instruments sales representative or local authorized distributor for more information.

 CDCE62002 CDCE62005CDCM61001 CDCM61002 CDCM61004 
VCC(V)3.3  3.3  3.3  3.3  3.3  
Input LevelLVPECL,LVDS,LVCMOS  LVPECL,LVDS,LVCMOS  Crystal or LVCMOS  Crystal or LVCMOS  Crystal or LVCMOS  
Output LevelLVPECL,LVDS,LVCMOS  LVPECL,LVDS,LVCMOS  LVPECL or LVDS or 2 LVCMOS  LVPECL or LVDS or 2 LVCMOS  LVPECL or LVDS or 2 LVCMOS  
No. of Outputs2  5  1  2  4  
Output Frequency(Min)(Mhz)10.94  4.25  43.75  43.75  43.75  
Output Frequency(Max)(Mhz)1175  1175  683.28  683.28  683.28  
Divider RatioUniversal  Universal  Universal  Universal  Universal  
RMS Jitter 1ps  500fs Typical, <1ps Max  500fs Typical, <1ps Max  500fs Typical, <1ps Max  
Operating Frequency Range(Min)(MHz)10.94  4.25  43.75  43.75  43.75  
Operating Frequency Range(Max)(MHz)1175  1175  683.28  683.28  683.28  
Output Skew(ps)75  75     
Voltage Range3.3  3.3  3.3  3.3  3.3  
Supply Current(mA)230   108mA Max  108mA Max  108mA Max  
 SamplesSamplesSamplesSamplesSamples
 InventoryInventoryInventoryInventoryInventory

Customers Who Evaluated This Product Also Evaluated

  • CDCE62002: Four Output Clock Generator/Jitter Cleaner with Integrated Dual VCOs
  • CDCM61004: 1:4 Ultra Low Jitter Crystal-In Clock Generator
  • CDCM61001: 1:1 Ultra Low Jitter Crystal-In Clock Generator
  • CDCE72010: 10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner
  • CDCM7005: High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO
  • CDCE913: Programmable 1-PLL VCXO Clock Synthesizer with 2.5-V or 3.3-V LVCMOS Outputs

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Product Information

Features

  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter.
  • Fully Configurable Outputs Including Frequency, Output Format, and Output Skew.
  • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs.
  • Multiple Operational Modes Include Clock Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power-up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode.
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz–2.356 GHz
  • Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or Combinations of Differential or Single-ended:
    • 0.35 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: -130 dBc/Hz at 1 MHz offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-out Mode
    • LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
    • Independent Output Dividers Support Divide Ratios from 1-80(1)
    • Independent Coarse Skew Control on all Outputs(2)
  • Flexible Inputs With Innovative Smart Multiplexer Feature:
    • Two Universal Differential Inputs Accept Frequencies in the Range of 40 kHz to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS).
    • One Auxiliary Input Accepts Single Ended Clock Source or Crystal. Auxiliary Input Accepts Crystals in the Range of
      2 MHz-42 MHz or an LVCMOS Input in the Range of 2 MHz to 75MHz.
    • Clock Generator Mode Using Crystal Input.
    • Smart Input Multiplexer can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-safe Operation and Holdover Modes.
  • Typical Power Consumption 1.7W at 3.3V
  • Integrated EEPROM Stores Default Settings; Therefore, The Device Can Power up in a Known, Predefined State.
  • Offered in QFN-48 Package
  • ESD Protection Exceeds 2kV HBM
  • Industrial Temperature Range -40°C to 85°C
  • APPLICATIONS
    • Data Converter and Data Aggregation Clocking
    • Wireless Infrastructure
    • Switches and Routers
    • Medical Electronics
    • Military and Aerospace
    • Industrial
    • Clock Generation and Jitter Cleaning

(1) Non-continuous values supported.
(2) The coarse skew control does not operate for reference input frequencies less than 1 MHz
(3) 10 kHz to 20 MHz integration bandwidth.
(4) Frequency range depends on operational mode and output format selected.

Description

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (3). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 125 kHz to 1.5 GHz (4)) and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode (e.g., LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 80 kHz to 500 MHz and an auxiliary single ended input that can be connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierSamples
CDCE62005RGZRACTIVE-40 to 857.50 | 1kuQFN (RGZ) | 48 View 2500 | LARGE T&RPurchase Samples
CDCE62005RGZTACTIVE-40 to 858.25 | 1kuQFN (RGZ) | 48 View 250 | SMALL T&R

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:03 PM GMT, 05 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 20 WeeksCDCE62005RGZR
None Reported
View Distributors
TI Lead Time*: 20 WeeksCDCE62005RGZT
AmericasAvnet 250
AsiaFarnell Asia 27
WPI 116
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
CDCE62005RGZR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HRViewView
CDCE62005RGZT RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

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Datasheet

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Simulation Models

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