CDCLVD110A Status: ACTIVE

1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution

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Datasheet

Progrmmable Low-Voltage 1:10 LVDS Clock Driver (Rev. C) (PDF 600 KB)
02 Nov 2009

	CDCLVD110A
Frequency(Max)(MHz)	1100
VCC(V)	2.5
Input Level	LVDS
No. of Outputs	10
Output Level	LVDS
Pin/Package	32LQFP, 32QFN
Operating Temp Range(Celsius)	-40 to 85
	Samples
	Inventory

Customers Who Evaluated This Product Also Evaluated

CDCLVP111: 1:10 LVPECL Buffer with Selectable Input
CDCL1810: 1.8V 1-to-10 High Performance Differential Clock Buffer
CDCE18005: 5/10 Outputs Clock Buffer with Divider
CDCE62005: 5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO
CDCE72010: 10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner

Product Information

Features

Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
V_CC range 2.5 V ±5%
Typical Signaling Rate Capability of Up to 1.1 GHz
Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
Full Rail-to-Rail Common-Mode Input Range
Receiver Input Threshold ±100 mV
Available in 32-Pin LQFP and QFN Package
Fail-Safe I/O-Pins for V_DD = 0 V (Power Down)
APPLICATIONS
- General purpose Industrial, Communication and Consumer Applications

Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0–Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50- transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110A has an improved startup circuit that minimizes enabling time in AC- and DC-coupled systems.

View All Description in Datasheet

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools		Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Symbols	Footprints	Samples
CDCLVD110ARHBR	ACTIVE	-40 to 85	5.90 \| 1ku	QFN (RHB) \| 32	View	3000 \| LARGE T&R			Purchase Samples
CDCLVD110ARHBRG4	ACTIVE	-40 to 85	5.90 \| 1ku	QFN (RHB) \| 32	View	3000 \| LARGE T&R			Purchase Samples
CDCLVD110ARHBT	ACTIVE	-40 to 85	6.50 \| 1ku	QFN (RHB) \| 32	View	250 \| SMALL T&R
CDCLVD110ARHBTG4	ACTIVE	-40 to 85	6.50 \| 1ku	QFN (RHB) \| 32	View	250 \| SMALL T&R
CDCLVD110AVF	ACTIVE	-40 to 85	6.50 \| 1ku	LQFP (VF) \| 32	View	250 \| JEDEC TRAY (10+1)
CDCLVD110AVFG4	ACTIVE	-40 to 85	6.50 \| 1ku	LQFP (VF) \| 32	View	250 \| JEDEC TRAY (10+1)
CDCLVD110AVFR	ACTIVE	-40 to 85	5.90 \| 1ku	LQFP (VF) \| 32	View	1000 \| LARGE T&R	Purchase Samples
CDCLVD110AVFRG4	ACTIVE	-40 to 85	5.90 \| 1ku	LQFP (VF) \| 32	View	1000 \| LARGE T&R	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 12:01 PM GMT, 22 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 20 WeeksCDCLVD110ARHBR
None Reported View Distributors
TI Lead Time*: 20 WeeksCDCLVD110ARHBRG4
None Reported View Distributors
TI Lead Time*: 16 WeeksCDCLVD110ARHBT
Asia	WPI	344
TI Lead Time*: 16 WeeksCDCLVD110ARHBTG4
None Reported View Distributors
TI Lead Time*: 20 WeeksCDCLVD110AVF
Asia	WPI	81
Worldwide	DigiKey	454
	Mouser Electronics	180
TI Lead Time*: 20 WeeksCDCLVD110AVFG4
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksCDCLVD110AVFR
Worldwide	DigiKey	Available
TI Lead Time*: 20 WeeksCDCLVD110AVFRG4
Worldwide	DigiKey	Available
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CDCLVD110ARHBR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVD110ARHBRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVD110ARHBT	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVD110ARHBTG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVD110AVF	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CDCLVD110AVFG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CDCLVD110AVFR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CDCLVD110AVFRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for CDCLVD110A

Datasheet

Progrmmable Low-Voltage 1:10 LVDS Clock Driver (Rev. C) (PDF, 600 KB)
02 Nov 2009

Simulation Models

IBIS Model
- CDCLVD110A IBIS Software (Multiple File Format) 137 views
  14 Feb 2008 Read Abstract

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CDCE18005	5/10 Outputs Clock Buffer with Divider	NON-PLL BUFFERS-MIXED SINGLE AND DIFFERENTIAL ENDED	TI customers also evaluated this product.
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CDCLVD110A Status: ACTIVE

1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution

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