CDCLVP111 Status: ACTIVE

1:10 LVPECL Buffer with Selectable Input

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Datasheet

LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER (Rev. C) (PDF 633 KB)
02 Nov 2009

	CDCLVP110	CDCLVP111	CDCLVP215	CDCVF111
Frequency(Max)(MHz)	3500	3500	3500	650
VCC(V)	2.5, 3.3	2.5, 3.3	2.5, 3.3	3.3
Input Level	HSTL, LVPECL	LVPECL,LVDS,CML,SSTL	LVPECL	LVPECL
No. of Outputs	10	10	10	9
Vcc range(V)	2.375 - 3.8	2.375 - 3.8	2.375 - 3.8
Output Level	LVPECL	LVPECL	LVPECL	LVPECL
Pin/Package	32LQFP	32LQFP, 32QFN	32QFN	28PLCC
Operating Temp Range(Celsius)	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Tsk(o)(ps)			30
	Samples	Samples	Samples	Samples
	Inventory	Inventory	Inventory	Inventory

Customers Who Evaluated This Product Also Evaluated

CDCLVP215: Dual 1:5 High Speed LVPECL Fan Out Buffer
CDCLVD110A: 1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution
DAC5689: 16-bit, 800 MSPS 2x-8x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)
DAC5675-EP: Enhanced Product 14-Bit 400-Msps Digital-To-Analog Converter
PTH04T240W: 10-A, 2.2V to 5.5V Input, Non-Isolated, Wide Output, Adjustable Power Module with TurboTrans

Product Information

Features

Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
Fully Compatible With LVECL/LVPECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 350 ps
- Open Input Default State
- LVDS, CML, SSTL input compatible
V_BB Reference Voltage Output for Single-Ended Clocking
Available in a 32-Pin LQFP and QFN Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
APPLICATIONS
- Designed for Driving 50 Transmission Lines
- High Performance Clock Distribution

Description

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50- transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 .

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

View All Description in Datasheet

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Samples
CDCLVP111RHBR	ACTIVE	-40 to 85	5.55 \| 1ku	QFN (RHB) \| 32	View	3000 \| LARGE T&R
CDCLVP111RHBT	ACTIVE	-40 to 85	6.15 \| 1ku	QFN (RHB) \| 32	View	250 \| SMALL T&R	Purchase Samples
CDCLVP111VF	ACTIVE	-40 to 85	5.55 \| 1ku	LQFP (VF) \| 32	View	250 \| JEDEC TRAY (10+1)
CDCLVP111VFR	ACTIVE	-40 to 85	5.55 \| 1ku	LQFP (VF) \| 32	View	1000 \| LARGE T&R	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 11:31 AM GMT, 09 Feb 2010
Region	Company	In Stock	Purchase
TI Lead Time*: 10 WeeksCDCLVP111RHBR
None Reported View Distributors
TI Lead Time*: 16 WeeksCDCLVP111RHBT
None Reported View Distributors
TI Lead Time*: 20 WeeksCDCLVP111VF
Americas	Arrow	250
Americas	Newark	250
Asia	Farnell Asia	249
Europe	Arrow Northern Europe	250
	Avnet-SILICA	250
	EBV Elektronik	125
	Farnell	249
Worldwide	Mouser Electronics	342
TI Lead Time*: 20 WeeksCDCLVP111VFR
None Reported View Distributors
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CDCLVP111RHBR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVP111RHBT	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	View	View
CDCLVP111VF	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
CDCLVP111VFR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for CDCLVP111

Datasheet

LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER (Rev. C) (PDF, 633 KB)
02 Nov 2009

Simulation Models

IBIS Model
- CDCLVP111 IBIS Model Version 2.0 (ZIP, 33 KB) 41 views
  02 Apr 2009

Part #	Name	Product Family	Comments
CDCLVP110	1:10 LVPECL/HSTL to LVPECL Clock Driver	NON-PLL BUFFERS - DIFFERENTIAL ENDED(NP)	The device has the SAME FUNCTIONALITY and PINOUT as the compared device but is NOT an exact equivalent. CDCLVP110 does not have pull-up/pull down resistor integrated
CDCLVP215	Dual 1:5 High Speed LVPECL Fan Out Buffer	NON-PLL BUFFERS - DIFFERENTIAL ENDED(NP)	The device has the SAME FUNCTIONALITY and PINOUT as the compared device but is NOT an exact equivalent. CDCLVP215 is a dual 1:5 buffer
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CDCLVP111 Status: ACTIVE

1:10 LVPECL Buffer with Selectable Input

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