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CDCU2A877 Status: ACTIVE

1.8V Phase-Lock Loop Clock Driver with high output drive for DDR2 SDRAM Applications

      
         
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Datasheet

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 CDCU2A877
VCC(V)1.8  
Operating Frequency Range(Min)(MHz)125  
Operating Frequency Range(Max)(MHz)410  
Absolute Jitter (cycle-to-cycle)(ps)30  
t(phase error)(Min)(ps)-35  
t(phase error)(Max)(ps)35  
Input LevelSSTL-18  
No. of Outputs10  
Output Drive(mA)18  
tsk(o)(ns)0.03  
Output LevelSSTL-18  
Pin/Package52BGA MICROSTAR JUNIOR  
Static Current(mA)0.5  
Operating Temp Range(Celsius)0 to 70  
 Samples
 Inventory

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Product Information

Features

  • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 125 MHz to 410 MHz
  • Application Frequency: 160 MHz to 410 MHz
  • Low Jitter (Cycle-Cycle): ±40 ps
  • Low Output Skew: 35 ps
  • Stabilization Time <6 µs
  • Distributes One Differential Clock Input to 10 Differential Outputs
  • High-Drive Version of CDCUA877
  • 52-Ball mBGA (MicroStar Junior™; BGA, 0,65-mm pitch)
  • External Feedback Pins ( FBIN, FBIN ) are Used to Synchronize the Outputs to the Input Clocks
  • Meets or Exceeds CUA877/CUA878 Specification PLL Standard for PC2-3200/4300/5300/6400
  • Fail-Safe Inputs

MicroStar Junior is a trademark of Texas Instruments.

Description

The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierSymbolsFootprintsSamples
CDCU2A877ZQLRACTIVE0 to 702.80 | 1kuBGA MICROSTAR JUNIOR (ZQL) | 52 View 1000 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
CDCU2A877ZQLTACTIVE0 to 703.05 | 1kuBGA MICROSTAR JUNIOR (ZQL) | 52 View 250 | SMALL T&R Download CAD Format for this Symbol Download CAD Format for this FootprintContact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
CDCU2A877ZQLRAs of 11:39 AM GMT, 03 Jul 2009As of 11:39 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 4 Weeks AmericasAvnet >1k
 DigiKey  Available
 Rochester Electronics 1k
CDCU2A877ZQLTAs of 11:39 AM GMT, 03 Jul 2009As of 11:39 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 8 Weeks AmericasDigiKey 80
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
CDCU2A877ZQLR RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEARViewView
CDCU2A877ZQLT RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEARViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

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Datasheet

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