DAC5675A-SP Status: ACTIVE

Class V, 14 Bit, 400 MSPS Digital-to-Analog Converter

      
         
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Datasheet

Download - PDF Icon
  • Class V 14-Bit 400-MSPS Digital-to-Analog Converter (Rev. C) (dac5675a-sp.pdf, 673 KB)
    05 Oct 2007 Download

Other qualified versions of DAC5675A-SP

Version Part Number Definition
Catalog DAC5675A TI's standard catalog product

Customers Who Evaluated This Product Also Evaluated

  • DAC5675A: 14-Bit, 400-MSPS Digital-to-Analog Converter
  • ADS5424-SP: Class V, 14 Bit, 105 MSPS Analog-to-Digital Converter

Product Information

Features

  • 400 MSPS Update Rate
  • LVDS-Compatible Input Interface
  • Spurious-Free Dynamic Range (SFDR) to Nyquist
    • 69 dBc at 70 MHz IF, 400 MSPS
  • W-CDMA Adjacent Channel Power Ratio (ACPR)
    • 73 dBc at 30.72 MHz IF, 122.88 MSPS
    • 71 dBc at 61.44 MHz IF, 245.76 MSPS
  • Differential Scalable Current Outputs:
    2 mA to 20 mA
  • On-Chip 1.2 V Reference
  • Single 3.3 V Supply Operation
  • Power Dissipation: 660 mW at fCLK = 400 MSPS, fOUT = 20 MHz
  • High-Performance 52 Pin Ceramic Quad Flat Pack (HFG)
  • Military Temperature Range (-55°C to 125°C)
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel:
      • CDMA: WCDMA, CDMA2000, IS-95
      • TDMA: GSM, IS-136, EDGE/GPRS
      • Supports Single-Carrier and Multicarrier Applications
    • Test and Measurement: Arbitrary Waveform Generation

DESCRIPTION/ORDERING INFORMATION

The DAC5675A is a 14 bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).

The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.

The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.

The DAC5675A is specifically designed for a differential transformer-coupled output with a 50 doubly-terminated load. With the 20 mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD - 1 to AVDD + 0.3 V.

An accurate on-chip 1.2 V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA. This provides 20 dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which reduces the standby power to approximately 18 mW.

The DAC5675A is available in a 52 pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of -55°C to 125°C.

    

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Technical Documents

Datasheets

  • Class V 14-Bit 400-MSPS Digital-to-Analog Converter (Rev. C) (dac5675a-sp.pdf, 673 KB)
    05 Oct 2007 Download

Application Notes

  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters (scaa092.htm, 9 KB)
    08 Jun 2008 Abstract
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 (scaa091.htm, 8 KB)
    02 Jun 2008 Abstract
  • Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm, 8 KB)
    24 May 2004 Abstract
  • Thermal and Electrical Properties of Selected Packaging Materials (sbfa010.htm, 8 KB)
    04 Oct 2000 Abstract
  • Superposition: The Hidden DAC Linearity Error (sbaa047.htm, 8 KB)
    02 Oct 2000 Abstract
  • What Designers Should Know About Data Converter Drift (sbaa046.htm, 8 KB)
    02 Oct 2000 Abstract
  • High Speed Data Conversion (sbaa045.htm, 8 KB)
    02 Oct 2000 Abstract

View Application Notes for Digital to Analog Converters

User Guides

View User Guides for Digital to Analog Converters

Simulation Models

  • IBIS Model
    • IBIS Model of DAC5675A (slam016.ibs, 58 KB)
      05 Feb 2008 ibis
    • | zip

More Literature

View More Literature for Digital to Analog Converters

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