• 500 MSPS Maximum Update RateDAC
• WCDMA ACPR
  • 1 Carrier: 76 dB Centered at 30.72-MHz IF, 245.76 MSPS
  • 1 Carrier: 73 dB Centered at 61.44-MHz IF, 245.76 MSPS
  • 2 Carrier: 72 dB Centered at 30.72-MHz IF, 245.76 MSPS
  • 4 Carrier: 64 dB Centered at 92.16-MHz IF, 491.52 MSPS
• Selectable 2×, 4×, 8×, and 16× Interpolation
  • Linear Phase
  • 0.05-dB Pass-Band Ripple
  • 80-dB Stop-Band Attenuation
  • Stop-Band Transition 0.4-0.6 f_DATA
• 32-Bit Programmable NCO
• On-Chip 2×-16× PLL Clock Multiplier With Bypass Mode
• Differential Scalable Current Outputs: 2 mA to 20 mA
• On-Chip 1.2-V Reference
• 1.8-V Digital and 3.3-V Analog Supplies
• 1.8-V/3.3-V CMOS Compatible Interface
• Power Dissipation: 950 mW at Full Maximum Operating Conditions
• Package: 100-Pin HTQFP
• APPLICATIONS
  • Cellular Base Transceiver Station Transmit Channel
    • CDMA: W-CDMA, CDMA2000, IS-95
    • TDMA: GSM, IS-136, EDGE/UWC-136
  • Baseband I and Q Transmit
  • Input Interface: Quadrature Modulation for Interfacing With Baseband Complex Mixing ASICs
  • Single-Sideband Up-Conversion
  • Diversity Transmit
  • Cable Modem Termination System

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The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, 8×, and 16×interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include high-speed digital data transmission in wired and wireless communication systems and high-frequency direct-digital synthesis DDS.

The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and enables the use of relaxed analog post-filtering.

Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable NCO.

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements.

In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF single-sideband spectrum presented to RF.

The 2×, 4×, 8×, and 16×1; interpolation filters are implemented as a cascade of half-band 2× interpolation filters. Unused filters for interpolation rates of less than 16×1; are shut off to reduce power consumption. The DAC5686 provides a full bypass mode, which enables the user to bypass all the interpolation and mixing.

The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer-coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2-dBm output power) are supported.

The DAC5686 operational modes are configured by programming registers through a serial interface. The serial interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as separate parallel streams on two data buses, or as a single interleaved data stream on one data bus.

An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the system power consumption.

The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the industrial temperature range of -40°C to 85°C.