GC4016 Status: ACTIVE

Product Information

Features

• Input rates up to 100 MSPS
• Four independent digital down convert (DDC) channels
• Single channel GC4011 and Dual channel GC4012 derivatives are available
• Independent decimation and resampling
• Independent tuning, phase and gain controls
• Input Crossbar Switch for:
  • Four 14 bit Inputs, or
  • Three 16 bit Inputs, or
  • Three 12 bit + 3 bit exponent inputs, or
  • Two 14 bit differential inputs.
• Decimation factors of
  • 32 to 16,384 in each channel
  • 16 to 32 by combining two channels
  • 8 to 16 by combining four channels
• Zero padding for lower decimation factors
• Resampler for arbitrary decimation factors
• Peak detection counters for AGC loop controls
• Outputs can be either:
  • Bit serial, or
  • Nibble serial (link port), or
  • Parallel port, or
  • Memory mapped registers
• 12, 16, 20, or 24 bit output samples
• 0.02 Hz tuning resolution
• >100 dB far band rejection
• >115 dB spur free dynamic range
• User programmable 21 tap and 63 tap decimate by two filters, independent per channel.
• Nyquist filtering for QPSK or QAM symbol data
• Resampler provides additional filtering and allows arbitrary input/output rate selections
• Microprocessor interface for control
• Built in diagnostics
• Application examples:
  • Four 4X oversampled GSM, DAMPS, or IS95 CDMA carriers,
  • Two 8X oversampled IS95 CDMA carriers, or
  • Two 2X oversampled 3.84MB UMTS carriers, or
  • One 4X oversampled 3.84MB UMTS carrier
• Core power consumption at 80 MHz, 2.5 volts:
  • 100 mW per DAMPS channel
  • 115 mW per GSM channel
  • 115 mW per IS95 channel
  • 620 mW per 3.84MB UMTS channel
• Industrial temperature range (-40C to +85C)
• GC4016-PB 160 ball PBGA
• (15mm by 15mm) package
• 3.3volt I/O voltage, 2.5volt core voltage
• JTAG Boundary Scan

Description

The GC4016 quad receiver chip contain four identical down-conversion circuits. Each downconvert circuit accepts a real sample rate up to 100 MHz, down converts a selected carrier frequency to zero, decimates the signal rate by a programmable factor ranging from 32 to 16,384 and then resamples the channel to adjust the sample rate up or down by an arbitrary factor. In the real output mode the output sample rate is doubled and the signal is output as a real signal centered at F_out/4. The channels may be combined to produce wider band and/or oversampled outputs or to process complex input data. The chip outputs the down-converted signals in any one of several formats (microprocessor, four serial lines, one TDM serial line, nibble, LINK, or 24 bit parallel port. The chip contains two user programmable output filters per path which can be used to arbitrarily shape the received data�s spectrum. These filters can be used as Nyquist receive filters for digital data transmission. The chip also contains a resampling filter to provide additional filtering and to allow the user complete flexibility in the selection of input and output sample rates.

Two downconverter paths can be merged to be used as a single complex input down-conversion circuit. Two paths may also be combined to support wider band output rates or oversampled outputs. Four paths may be combined to support both wider band output and oversampling.

The downconverters are designed to maintain over 115 dB of spur free dynamic range and over 100 dB of out of band rejection. A five stage CIC and 20 bit internal datapaths support this high dynamic range signal processing requirement. Each downconvert circuit accepts 16 bit inputs and produces 24 bit outputs (can be rounded back to 12, 16, or 20 bits). The frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can the decimation and filter parameters of each circuit.

On chip diagnostic circuits are provided to simplify system debug and maintenance.

The chip receives configuration and control information over a microprocessor compatible bus consisting of an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip�s control registers (8 bits each) are memory mapped into the 5 bit address space of the control port.

Sections 7.9 through 7.12 describe how to use the chip for GSM, D-AMPS, CDMA and UMTS applications, including control register values and filter coefficients.