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GC5322: Wideband Transmit IC Solution with integrated Digital Predistortion, Digital Upconversion,
GC5325: Wideband Digital Predistortion Transmit Processor
Product Information
Features
Integrated DUC, CFR, and DPD Solution
20-MHz Max. Signal Bandwidth, Based on Max. DPD Clock of 200 Mhz, Fifth-Order Correction
DUC: Up to 12 CDMA2000/TDSCDMA, 4 W-CDMA, 2–10 MHz or 1–20 MHz OFDMA Carriers
CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB PAR, < 8.5 dB PAR for OFDMA Signals
DPD: Short-Term Memory Compensation, Typical ACLR Improvement > 20 dB
GC5328IZER PBGA Package, 23 mm × 23 mm
1.2-V Core, 1.8-V HSTL, 3.3-V I/O
2.5-W Typical Power Consumption
TMS320C6727 DPD Optimization Software
Supports Direct Interface to TI High-Speed Data Converters
APPLICATIONS
3 GPP (W-CDMA) Base Stations
3 GPP2 (CDMA2000) Base Stations
WiMAX, WiBRO, and LTE (OFDMA) Base Stations
Multicarrier Power Amplifiers (MCPAs)
Description
The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion (DPD) block, feedback (FB) block, and capture buffer (CB) blocks.
The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined IQ signal. The DUC provides three stages of interpolation and a complex mixer. There are two DUC blocks. The output from the DUC blocks is combined in the sum chain. Each of the 1 to 12 DUC channels can be summed, and the composite signal can be scaled.
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Inventory
Reported Distributor Inventory as of 11:59 AM GMT, 25 Nov 2009
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