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OMAP-L137 Status: ACTIVE

Low-Power Applications Processor


      
         
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See Also

  • TMS320C6747 - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device. 
  • TMS320C6745 - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device. 
  • TMS320C6743 - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device. 

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Datasheet

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Functional Block Diagram


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 OMAP-L137
CPU1 C674x; 1 ARM9  
Peak MMACS2400  
RISC Frequency(MHz)300  
Frequency(MHz)300  
On-Chip L1/SRAM64 KB  
On-Chip L2/SRAM256 KB  
ROM1024 KB  
EMIF1 16/8-Bit EMIFA,32/16-Bit EMIFB  
External Memory Type SupportedAsync SRAM,SDRAM,NAND Flash,NOR  
DMA32-Ch EDMA  
EMAC10/100  
HPI1 16-bit  
LCD1  
MMC/SD1  
I2C2  
SPI2  
UART3  
USB1  
PWM3  
eCAP3  
McASP3  
Timers1 64-Bit GP,1 64-Bit GP/WD  
RTC1  
Core Supply (Volts)1.2 V  
IO Supply (Volts)1.8 V,3.3 V  
Operating Temperature Range (°C)0 to 70,-40 to 125  
 Samples
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Product Information

Features

  • Applications
    • Industrial Control
    • USB, Networking
    • High-Speed Encoding
    • Professional Audio
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • Dual Core SoC
    • 300-MHz ARM926EJ-S™ RISC MPU
    • 300-MHz C674x VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
  • C674x Instruction Set Features
    • Superset of the C67x+™ and C64x+™ ISAs
    • 2400/1800 C674x MIPS/MFLOPS
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two Level Cache Memory Architecture
    • 32K-Byte L1P Program RAM/Cache
    • 32K-Byte L1D Data RAM/Cache
    • 256K-Byte L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
    • 1024K-Byte L2 ROM
  • Enhanced Direct-Memory-Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x™ Floating Point VLIW DSP Core
    • Load-Store Architecture With Non-Aligned Support
    • 64 General-Purpose Registers (32 Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP × SP -> SP Per Clock
        • 2 SP × SP -> DP Every Two Clocks
        • 2 SP × DP -> DP Every Three Clocks
        • 2 DP × DP -> DP Every Four Clocks
      • Fixed Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Comples Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128K-Byte RAM Shared Memory
  • 3.3V LVCMOS IOs (except for USB interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8-/16-Bit-Wide Data)
      • NAND (8-/16-Bit-Wide Data)
      • 16-Bit SDRAM With 128MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM With 256MB Address Space
  • Three Configurable 16550 type UART Modules:
    • UART0 With Modem Control Signals
    • 16-byte FIFO
    • 16× or 13× Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
  • USB 1.1 OHCI (Host) With Integrated PHY (USB1)
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High-/Full-Speed Client
    • USB 2.0 High-/Full-/Low-Speed Host
    • End Point 0 (Control)
    • End Point 1,2,3,4 (Control, bulk, Interrupt or ISOC) Rx and Tx
  • Three Multichannel Audio Serial Ports:
    • Transmit/Receive Clocks up to 50 MHz
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO buffers for Transmit and Receive
  • 10/100 Mb/s Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Timer (Watch Dog)
  • Three Enhanced Pulse Width Modulators (eHRPWM):
    • Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture Modules (eCAP):
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs
    • Single Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Two 32-Bit Enhanced Quadrature Encoder
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial or Extended Temperature

DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.

Description

The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS ); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsPackage QTY | Package CarrierSamples
XOMAPL137AZKB3ACTIVE 21.65 | 100uBGA (ZKB) | 256 90Purchase Samples
XOMAPL137AZKBT3ACTIVE 25.30 | 100uBGA (ZKB) | 256 90Purchase Samples
XOMAPL137ZKB3ACTIVE0 to 7021.65 | 100uBGA (ZKB) | 256 90Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 11:42 AM GMT, 08 Nov 2009
RegionCompanyIn StockPurchase
Call**XOMAPL137ZKB3
AmericasArrow 62
Newark 72
AsiaWPI 120
EuropeAvnet-SILICA 47
EBV Elektronik 7
WorldwideMouser Electronics 56
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** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
XOMAPL137AZKB3  TBD Call TI Call TIViewView
XOMAPL137AZKBT3  TBD Call TI Call TIViewView
XOMAPL137ZKB3  TBD Call TI Call TIViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

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Datasheet

Application Notes

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User Guides

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Selection Guides

White Papers

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Errata

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Tools & Software

NamePart # Company Tool / Software Type
Software Development Kit (SDK) for OMAP-L1x and TMS320C674x DevicesSDK-OMAPLXC674XTexas InstrumentsDevelopment Platforms
XDS510 Class EmulatorsXDS510Texas InstrumentsEmulators/Analyzers
OMAP-L137/TMS320C6747 Floating Point Starter KitTMDXOSKL137BETTexas InstrumentsStarter Kits
TMS320C674x DSP LibrarySPRC900 Texas Instruments Signal Processing Libraries 
C64x+ Image Library (IMGLIB)SPRC264 Texas Instruments Signal Processing Libraries 
TMS320C67x DSP LibrarySPRC121 Texas Instruments Signal Processing Libraries 
C64x+ IQMath Library - A Virtual Floating Point EngineSPRC542 Texas Instruments Signal Processing Libraries 
C67x Fast Run-Time Support (RTS) LibrarySPRC060 Texas Instruments Signal Processing Libraries 
eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDMTMDXDAISXDM Texas Instruments Algorithms / Codecs 
C64x+ DSP Library (DSPLIB)SPRC265 Texas Instruments Signal Processing Libraries 
Multimedia Framework Products (MFP) - Codec Engine and xDAIS Framework ComponentsTMDMFP Texas Instruments Framework Software 

Simulation Models

View Simulation Models for OMAP-L1x Processors

Part # Name Product Family Comments
TMS320C6747   Floating-Point Digital Signal Processor   C6000 FLOATING/FIXED-POINT DSPS - TMS320C674X LOW POWER DSPS   The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   
TMS320C6745   Floating-Point Digital Signal Processor   C6000 FLOATING/FIXED-POINT DSPS - TMS320C674X LOW POWER DSPS   The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   
TMS320C6743   Fixed/Floating-Point Digital Signal Processor   C6000 FLOATING/FIXED-POINT DSPS - TMS320C674X LOW POWER DSPS   The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   
OMAP-L138   Low-Power Applications Processor   OMAP™ Applications Processors - OMAP-Lx Processors   The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   
TLV320AIC3107   Low-Power Stereo CODEC with Integrated Mono Class-D Amplifier   AUDIO CONVERTER AND CODEC - CODEC      
TLV320AIC3204   Very Low-Power Stereo Audio CODEC with Power TuneTM Technology   AUDIO CONVERTER AND CODEC - CODEC      
TLV320AIC36   Low Power Stereo Audio Codec for Portable Audio/Telephony   AUDIO CONVERTER AND CODEC - CODEC      
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