OMAP3530 Status: ACTIVE

Applications Processor

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Datasheet

OMAP3530/25 Applications Processor (Rev. D) (PDF 3729 KB) 387 views
22 May 2009
OMAP3530/25/15/03 Applications Processor Silicon Errata-Revs 3.1, 3.0, 2.1,&2.0 (Rev. D) (PDF 512 KB) 10816 views
18 Mar 2009

	OMAP3530
CPU	1 64x+,ARM Cortex-A8
Peak MMACS	3440
RISC Frequency(MHz)	600
Frequency(MHz)	430
On-Chip L1/SRAM	112 KB (DSP),32 KB (ARM Cortex-A8)
RAM	64 KB
On-Chip L2/SRAM	96 KB (DSP),256 KB (ARM Cortex-A8)
ROM	16 KB (DSP),32 KB (ARM Cortex-A8)
EMIF	1 32-Bit SDRC,1 16-Bit GPMC
External Memory Type Supported	LPDDR,NOR Flash,NAND flash,OneNAND,Asynch SRAM
DMA	64-Ch EDMA,32-Bit Channel SDMA
Video Port (Configurable)	1 Dedicated Output,1 Dedicated Input
Graphics Accelerator	1
MMC/SD	3
McBSP	5
Pin/Package	423FCBGA, 515POP-FCBGA
POP Interface	Yes (CBB)
I2C	3
McSPI	4
HDQ/1-Wire	1
UART	3
USB	1 USB 2.0 HS 3-Port,1 USB 2.0 HS OTG
Timers	12 32-Bit GP,2 32-Bit WD
Core Supply (Volts)	0.8 V to 1.35 V
IO Supply (Volts)	1.8 V,3.0 V (MMC1 Only)
Operating Temperature Range (°C)	0 to 90,-40 to 105
	Samples
	Inventory

Customers Who Evaluated This Product Also Evaluated

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Product Information

Features

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
OMAP3530/25 Applications Processor:
- OMAP™ 3 Architecture
- MPU Subsystem
  - 600-MHz ARM Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
  - 430-MHz TMS320C64x+™ DSP Core
  - Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
  - Video Hardware Accelerators
- POWERVR SGX™ Graphics Accelerator (OMAP3530 Device Only)
  - Tile Based Architecture delivering 10 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine Grained Task Switching, Load Balancing, and Power Management
  - Programmable High Quality Image Anti-Aliasing
- Fully Software-Compatible With C64x and ARM9™
- Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
  - +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Operation
C64x+ L1/L2 Memory Architecture
- 32K-Byte L1P Program RAM/Cache (Direct Mapped)
- 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
- 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
- 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation. Bit-Counting
- Compact 16-Bit Instructions
- Additional Instructions to Support Complex Multiplies
ARM Cortex™-A8 Core
- ARMv7 Architecture
  - Trust Zone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON™ Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
ARM Cortex™-A8 Memory Architecture:
- 16K-Byte Instruction Cache (4-Way Set-Associative)
- 16K-Byte Data Cache (4-Way Set-Associative)
- 256K-Byte L2 Cache
112K-Byte ROM
64K-Byte Shared SRAM
Endianess:
- ARM Instructions - Little Endian
- ARM Data — Configurable
- DSP Instuction/Data - Little Endian
External Memory Interfaces:
- SDRAM Controller (SDRC)
  - 16, 32-bit Memory Controller With 1G-Byte Total Address Space
  - Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
  - SDRAM Memory Scheduler (SMS) and Rotation Engine
- General Purpose Memory Controller (GPMC)
  - 16-bit Wide Multiplexed Address/Data Bus
  - Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
  - Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)
Camera Image Signal Processing (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- RAW Data Interface
- BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
- A-Law Compression and Decompression
- Preview Engine for Real-Time Image Processing
- Glueless Interface to Common Video Decoders
- Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate horizontal/Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC/PAL Video
  - Luma/Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
  - 5K-Byte Transmit/Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128 Channel Transmit/Receive Mode
- Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
- High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
- High-Speed/Full-Speed/Low-Speed Multiport USB Host Controller
  - 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
  - Supports Transceiverless Link Logic (TLL)
- One HDQ/1-Wire Interface
- Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex™ Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE-1149.1 (JTAG) Boundary-Scan Compatible
- Embedded Trace Macro Interface (ETM)
- Serial Data Transport Interface (SDTI)
11 32-bit General Purpose Timers
2 32-bit Watchdog Timers
1 32-bit 32-kHz Sync Timer
Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
65-nm CMOS Technology
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Descreet Memory Interface (Not Available in CBC Package)
Packages:
- 515-pin s-PBGA Package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)
- 515-pin s-PBGA Package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
- 423-pin s-PBGA Package (CUS Suffix), .65mm Ball Pitch
1.8-V I/O and 3.0-V (MMC1 only), 0.975-V to 1.35-V Adaptive Processor Core Voltage, 0.975-V to 1.35-V Adaptive Core Logic Voltage
Applications:
- Portable Navigation Devices
- Portable Media Player
- Advanced Portable consumer Electronics
- Digital TV
- Digital Video Camera
- Portable Data Collection
- Point-of-Sale Devices
- Gaming
- Web Tablet
- Smart White Goods
- Ultra Mobile Devices

All trademarks are the property of their respective owners.

Description

OMAP3530 and OMAP3525 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture. The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video
3D mobile gaming
Video conferencing
High-resolution still image
Video capture in 2.5G wireless terminals, 3G wireless terminals, and rich multimedia-featured handsets, and high-performance personal digital assistants (PDAs).

The device supports high-level operating systems (OSs), such as:

Windows CE
Symbian OS
Linux
Palm OS

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
SGX530 subsystem for 3D graphics acceleration to support display and gaming effects (3530 only)
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption.
Memory stacking feature using the package-on-package (POP) implementation (CBB package only)

OMAP3530/25 devices are available in a 515-pin PBGA package (CBB suffix) and a 423-pin PBGA package (CUS suffix). Some features of the CBB package are not available in the CUS package.

Pricing / Packaging / CAD Design Tools / Samples

		Price	Packaging		Samples
Device	Status	Price \| Quantity	Package \| Pins	Package QTY \| Package Carrier	Samples
OMAP3530DCBB	ACTIVE	46.10 \| 100u	POP-FCBGA (CBB) \| 515	168	Purchase Samples
OMAP3530DCBBA	ACTIVE	55.30 \| 100u	POP-FCBGA (CBB) \| 515	119	Purchase Samples
OMAP3530DCBC	ACTIVE	46.10 \| 100u	POP-FCBGA (CBC) \| 515	119	Purchase Samples
OMAP3530DCBCA	ACTIVE	55.30 \| 100u	POP-FCBGA (CBC) \| 515	119	Purchase Samples
OMAP3530DCUS	ACTIVE	46.10 \| 100u	FCBGA (CUS) \| 423	90	Purchase Samples
OMAP3530DCUSA	ACTIVE	55.30 \| 100u	FCBGA (CUS) \| 423	1	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
OMAP3530DCBB	Green (RoHS & no Sb/Br)	Call TI	Level-3-260C-168 HR	View	View
OMAP3530DCBBA	TBD	Call TI	Call TI	View	View
OMAP3530DCBC	TBD	Call TI	Call TI	View	View
OMAP3530DCBCA	TBD	Call TI	Call TI	View	View
OMAP3530DCUS	Green (RoHS & no Sb/Br)	Call TI	Level-3-260C-168 HR	View	View
OMAP3530DCUSA	TBD	Call TI	Call TI	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents TI Recommends

Most useful technical documents for OMAP3530

Simulation Models

IBIS Model
- OMAP3530/25 CBC IBIS Model (Multiple File Format) 268 views
  04 Sep 2008 Read Abstract
- OMAP3530/25 CBB IBIS Model (Multiple File Format) 417 views
  04 Sep 2008 Read Abstract
BSDL Model
- OMAP3530/25 CBB BSDL Model (Rev. B) (ZIP 10 KB) 554 views
  21 Jan 2009
- OMAP3530/25 CUS BSDL Model (Rev. A) (ZIP 9 KB) 456 views
  15 Jan 2009
- OMAP3530/25 CBC BSDL Model (ZIP 9 KB) 102 views
  06 Jan 2009
- OMAP3530/25 CUS IBIS Model (Rev. A) (Multiple File Format) 384 views
  06 Jan 2009 Read Abstract

View Simulation Models for OMAP35x Processors

White Papers

ARM The Cortex-A8 Microprocessor - White Paper (Rev. A) (PDF 77 KB) 6546 views
11 Mar 2008
SmartReflex(TM) Power & Performance Management Technologies (Rev. A) (PDF 259 KB) 2360 views
19 Feb 2008
Introduction to Graphics Software Development for OMAP 2/3 - White Paper (PDF 1061 KB) 5227 views
26 Feb 2008

View White Papers for OMAP35x Processors

Errata

OMAP3530/25/15/03 Applications Processor Silicon Errata-Revs 3.1, 3.0, 2.1,&2.0 (Rev. D) (PDF 512 KB) 10816 views
18 Mar 2009

More Literature

OMAP3530-25-15-03 CUS OrCad Symbol (Rev. A) (ZIP 10 KB) 1179 views
22 Jul 2008
OMAP35x Applications Processors Product Bulletin (Rev. B) (PDF 147 KB) 9495 views
10 Jun 2009
Picture it: DSPs in medical imaging (PDF 872 KB) 1211 views
08 Sep 2008
OMAP35x For Medical Apps (PDF 208 KB) 1608 views
25 Jul 2008
OMAP3530-25-15-03 CBB OrCad Symbol (ZIP 10 KB) 950 views
01 May 2008
OMAP3530-15-25-03 CUS Allegro Footprint (ZIP 57 KB) 920 views
01 May 2008
OMAP3530-15-25-03 CBB Allegro Footprint (ZIP 91 KB) 759 views
01 May 2008

Name	Part #	Company	Tool / Software Type
Code Composer Studio IDE	CCSTUDIO	Texas Instruments	Code Composer Studio(TM) IDE
OMAP35x Evaluation Module (EVM)	TMDXEVM3503	Texas Instruments	Development Boards/EVMs
XDS510 Class Emulators	XDS510	Texas Instruments	Emulators/Analyzers
Windows CE EVM Software (OS and BSP)	S1SDKWCE	Texas Instruments	Operating Systems (OS/RTOS)
QNX Neutrino RTOS		QNX Software Systems	Operating Systems (OS/RTOS)
Drivers/Platform Support Package (PSP)	SUPPORTPKG	Texas Instruments	Drivers / IO / Control Software

Part #	Name	Product Family	Comments
SN65LVDS315	CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER	DISPLAY INTERFACE - FLATLINK (LVDS FOR LCD)
SN65LVDS301	Programmable 27-Bit Display Serial Interface Transmitter	DISPLAY INTERFACE - FLATLINK (LVDS FOR LCD)
TPS62350	1A, 3MHz Buck Converter with I2C for Dynamic Voltage Scaling	DC/DC CONVERTERS (INTEGRATED SWITCH) - STEP-DOWN REGULATORS	Complementary Analog Part
TPS65023	6-channel Power Mgmt IC with 3DC/DCs, 3 LDOs, I2C Interface and DVS, Optimized for DaVinci DSPs	POWER MANAGEMENT MULTI-CHANNEL IC (PMIC) SOLUTIONS - PMIC SOLUTIONS WITH AND WITHOUT BATTERY CHARGER	Complementary Analog Part
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OMAP3530 Status: ACTIVE

Applications Processor

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Datasheet

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