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OMAP3530 Status:ACTIVE

Applications Processor

      
         
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Datasheet

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  • OMAP3530/25 Applications Processor (Rev. B) (omap3530.pdf, 3732 KB)
    29 Jul 2008 Download
  • OMAP3530/3525/3515/3503 Silicon Errata (Rev. A) (sprz278a.pdf, 352 KB)
    19 Jun 2008 Download

 OMAP3530
CPU1 64x+,ARM Cortex-A8  
Peak MMACS3440  
RISC Frequency(MHz)600  
Frequency(MHz)430  
On-Chip L1/SRAM112 KB (DSP),32 KB (ARM Cortex-A8)  
RAM64 KB  
On-Chip L2/SRAM96 KB (DSP),256 KB (ARM Cortex-A8)  
ROM16 KB (DSP),32 KB (ARM Cortex-A8)  
EMIF1 32-Bit SDRC,1 16-Bit GPMC  
External Memory Type SupportedLPDDR,NOR Flash,NAND flash,OneNAND,Asynch SRAM  
DMA64-Ch EDMA,32-Bit Channel SDMA  
Video Port (Configurable)1 Dedicated Output,1 Dedicated Input  
Graphics Accelerator1  
MMC/SD3  
McBSP5  
Pin/Package423FCBGA,515FCBGA  
POP InterfaceYes (CBB)  
I2C3  
McSPI4  
HDQ/1-Wire1  
UART3  
USB1 USB 2.0 HS 3-Port,1 USB 2.0 HS OTG  
Timers12 32-Bit GP,2 32-Bit WD  
Core Supply (Volts)0.8 V to 1.35 V  
IO Supply (Volts)1.8 V,3.0 V (MMC1 Only)  
Operating Temperature Range (°C)0 to 90  
 Samples
 Inventory

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Product Information

Features

  • OMAP3530/25 Applications Processor:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • 600-MHz ARM Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
      • 430-MHz TMS320C64x+™ DSP Core
      • Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
      • Video Hardware Accelerators
    • 2D/3D Graphics Accelerator (OMAP3530 Device Only)
      • Tile Based Architecture delivering 10 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 and Direct3D Mobile
      • Fine Grained Task Switching, Load Balancing, and Power Management
      • Programmable High Quality Image Anti-Aliasing
    • Fully Software-Compatible With C64x and ARM9™
    • Commercial and Extended Temperature Grades
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
    • 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation. Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • ARM Cortex™-A8 Core
    • ARMv7 Architecture
      • Trust Zone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON™ Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
  • ARM Cortex™-A8 Memory Architecture:
    • 16K-Byte Instruction Cache (4-Way Set-Associative)
    • 16K-Byte Data Cache (4-Way Set-Associative)
    • 256K-Byte L2 Cache
  • 112K-Byte ROM
  • 64K-Byte Shared SRAM
  • Endianess:
    • ARM Instructions - Little Endian
    • ARM Data — Configurable
    • DSP Instuction/Data - Little Endian
  • External Memory Interfaces:
    • SDRAM Controller (SDRC)
      • 16, 32-bit Memory Controller With 1G-Byte Total Address Space
      • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
      • SDRAM Memory Scheduler (SMS) and Rotation Engine
    • General Purpose Memory Controller (GPMC)
      • 16-bit Wide Multiplexed Address/Data Bus
      • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
      • Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)
  • Camera Image Signal Processing (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • RAW Data Interface
    • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
    • A-Law Compression and Decompression
    • Preview Engine for Real-Time Image Processing
    • Glueless Interface to Common Video Decoders
    • Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate horizontal/Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC/PAL Video
      • Luma/Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
      • 5K-Byte Transmit/Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128 Channel Transmit/Receive Mode
    • Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
    • High-Speed/Full-Speed/Low-Speed Multiport USB Host Controller
      • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
      • Supports Transceiverless Link Logic (TLL)
    • One HDQ/1-Wire Interface
    • Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
    • Embedded Trace Macro Interface (ETM)
    • Serial Data Transport Interface (SDTI)
  • 12 32-bit General Purpose Timers
  • 2 32-bit Watchdog Timers
  • 1 32-bit 32-kHz Sync Timer
  • Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 65-nm CMOS Technology
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Descreet Memory Interface (Not Available in CBC Package)
  • Packages:
    • 515-pin PBGA Package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)
    • 515-pin S-PBGA Package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
    • 423-pin PBGA Package (CUS Suffix), .65mm Ball Pitch
  • 1.8-V I/O and 3.0-V (MMC1 only), 0.8-V to 1.35-V Adaptive Core Voltage, 0.8-V to 1.15-V Adaptive Core Logic Voltage
  • Applications:
    • Portable Navigation Devices
    • Portable Media Player
    • Advanced Portable consumer Electronics
    • Digital TV
    • Digital Video Camera
    • Portable Data Collection
    • Point-of-Sale Devices
    • Gaming
    • Web Tablet
    • Smart White Goods
    • Ultra Mobile Devices

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Description

OMAP3530 and OMAP3525 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture. The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • 2D/3D mobile gaming
  • Video conferencing
  • High-resolution still image
  • Video capture in 2.5G wireless terminals, 3G wireless terminals, and rich multimedia-featured handsets, and high-performance personal digital assistants (PDAs).

The device supports high-level operating systems (OSs), such as:

  • Windows CE
  • Symbian OS
  • Linux
  • Palm OS

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
  • IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
  • SGX530 subsystem for 2D and 3D graphics acceleration to support display and gaming effects (3530 only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory stacking feature using the package-on-package (POP) implementation (CBB package only)

OMAP3530/25 devices are available in a 515-pin PBGA package (CBB suffix) and a 423-pin PBGA package (CUS suffix). Some features of the CBB package are not available in the CUS package.

    

Pricing / Packaging / CAD Design Tools / Samples

Price ($US)PackagingSamples
DeviceStatusPrice ($US) | QuantityPackage | PinsPackage QTY | Package CarrierSamples
XOMAP3530BCBBACTIVE58.00 | 100uFCBGA (CBB) | 515 168Purchase Samples
XOMAP3530BCUSACTIVE58.00 | 100uFCBGA (CUS) | 423 90Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
XOMAP3530BCBBAs of 8:49 AM GMT, 29 Aug 2008As of 8:49 AM GMT, 29 Aug 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasDigiKey 108
  Mouser Electronics 2
  EuropeEBV Elektronik 1
XOMAP3530BCUSAs of 8:49 AM GMT, 29 Aug 2008As of 8:49 AM GMT, 29 Aug 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasMouser Electronics 1
View all Distributors  

* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
XOMAP3530BCBB  TBD Call TI Call TIViewView
XOMAP3530BCUS  TBD Call TI Call TIViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents TI Recommends - Technical Documentation TI Recommends

Datasheets

  • OMAP3530/25 Applications Processor (Rev. B) (omap3530.pdf, 3732 KB)
    29 Jul 2008 Download
  • OMAP3530/3525/3515/3503 Silicon Errata (Rev. A) (sprz278a.pdf, 352 KB)
    19 Jun 2008 Download

Application Notes

  • OMAP35x 0.65mm Pitch Layout Methods (Rev. B) (spraav6b.htm, 8 KB)
    26 Jun 2008 Abstract
  • PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part I (spraav1.htm, 9 KB)
    19 May 2008 Abstract
  • PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (spraav2.htm, 9 KB)
    29 Apr 2008 Abstract

View Application Notes for OMAP35x Processors

User Guides

  • OMAP35xx Technical Reference Manual (Rev. A) (spruf98a.htm, 8 KB)
    17 Apr 2008 Abstract
  • OMAP35xx Peripherals Overview Reference Guide (sprufn0.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Memory Subsystem Reference Guide (TRM Ch 11) (Rev. A) (sprufa1a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx MMC/SD/SDIO Card Interface Reference Guide (TRM Ch 22) (Rev. A) (sprufd2a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Multichannel Buffered Serial Port (McBSP) Reference Guide (TRM Ch 21) (Rev. A) (sprufd1a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Timers Reference Guide (TRM Ch 16) (Rev. A) (sprufa9a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx 2D/3D Graphics Accelerator (SGX) Reference Guide (TRM Ch 13) (Rev. A) (spruff6a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx IVA2.2 Subsystem Reference Guide (TRM Ch 14) (Rev. A) (sprufa3a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Memory Management Units (MMUs) Reference Guide (TRM Ch 8) (Rev. A) (spruff5a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx MPU Subsystem Reference Guide (TRM Ch 3) (Rev. A) (sprufa0a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Applications Processor Introduction Reference Guide (TRM Ch 1) (Rev. A) (spruff1a.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Interconnect Reference Guide (TRM Ch 5) (spruff3.htm, 8 KB)
    14 Apr 2008 Abstract
  • OMAP35xx Universal Serial Bus (USB) Reference Guide (TRM Ch 23) (sprufd4.htm, 8 KB)
    13 Mar 2008 Abstract
  • OMAP35xx Interprocessor Communication (IPC) Module Reference Guide (TRM Ch 6) (spruff4.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Memory Mapping Reference Guide (TRM Ch 2) (spruff2.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Applications Processor Initialization Reference Guide (TRM Ch 25) (sprufd6.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx General-Purpose I/O (GPIO) Interface Reference Guide (TRM Ch 24) (sprufd5.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx HDQ/1-Wire Module Reference Guide (TRM Ch 20) (sprufd0.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Multichannel Serial Port Interface (McSPI) Reference Guide (TRM Ch 19) (sprufc9.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Inter-Integrated Circuit (I2C) Module Reference Guide (TRM Ch 18) (sprufc6.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx UART/IrDA/CIR Module Reference Guide (TRM Ch 17) (sprufc5.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Interrupt Controller (INTC) Reference Guide (TRM Ch 10) (sprufa8.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx System Direct Memory Access (SDMA) Reference Guide (TRM Ch 9) (sprufa7.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx System Control Module Reference Guide (TRM Ch 7) (sprufa6.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Power, Reset, and Clock Management Reference Guide (TRM Ch 4) (sprufa5.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Display Interface Subsystem Reference Guide (TRM Ch 15) (sprufa4.htm, 8 KB)
    26 Feb 2008 Abstract
  • OMAP35xx Camera Interface Subsystem (ISP) Reference Guide (TRM Ch 12) (sprufa2.htm, 8 KB)
    26 Feb 2008 Abstract

View User Guides for OMAP35x Processors

Simulation Models

  • BSDL Model
    • OMAP3530/25 CBB BSDL Model (Rev. A) (sprm315a.zip, 10 KB)
      27 Jun 2008 zip
    • OMAP3530/25 CUS BSDL Model (sprm314.zip, 9 KB)
      10 Mar 2008 zip

View Simulation Models for OMAP35x Processors

White Papers

  • ARM The Cortex-A8 Microprocessor - White Paper (Rev. A)  (spry112a.pdf, 77 KB)
    11 Mar 2008  Download
  • Introduction to Graphics Software Development for OMAP 2/3 - White Paper  (spry110.pdf, 1061 KB)
    26 Feb 2008  Download
  • SmartReflex(TM) Power & Performance Management Technologies (Rev. A)  (swpy015a.pdf, 259 KB)
    19 Feb 2008  Download

View White Papers for OMAP35x Processors

More Literature

  • OMAP35x For Medical Apps (sprt491.pdf, 206 KB)
    25 Jul 2008 Download
  • OMAP35x Applications Processors Product Bulletin (Rev. A) (sprt457a.pdf, 115 KB)
    25 Jul 2008 Download
  • OMAP3530-25-15-03 CUS OrCad Symbol (Rev. A) (sprr095a.zip, 10 KB)
    22 Jul 2008 zip
  • OMAP3530-25-15-03 CBB OrCad Symbol (sprr094.zip, 10 KB)
    01 May 2008 zip
  • OMAP3530-15-25-03 CUS Allegro Footprint (sprr093.zip, 57 KB)
    01 May 2008 zip
  • OMAP3530-15-25-03 CBB Allegro Footprint (sprr092.zip, 91 KB)
    01 May 2008 zip

View More Literature for OMAP35x Processors

Tools & Software

NamePart # Company Tool / Software Type
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
OMAP35x Evaluation Module (EVM)TMDXEVM3503Texas InstrumentsDevelopment Boards/EVMs
Zoom OMAP35x Medical Development KitTMDXMEVM3503-LTexas InstrumentsDevelopment Platforms

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