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SN54ACT8990 Status: ACTIVE

Test Bus Controllers


      
         
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 SN54ACT8990SN74ACT8990 
Voltage Nodes(V)5  5  
Vcc range(V)4.5 to 5.5  4.5 to 5.5  
Input LevelTTL  TTL  
Output LevelCMOS  CMOS  
RatingMilitary  Catalog  
Technology FamilyJTAG  JTAG  
 SamplesSamples
 InventoryInventory

Other qualified versions of SN54ACT8990

Version Part Number Definition
Catalog SN74ACT8990 TI's standard catalog product

Product Information

Features

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Control Operation of Up to Six Parallel Target Scan Paths
  • Accommodate Pipeline Delay to Target of Up to 31 Clock Cycles
  • Scan Data Up to 232 Clock Cycles
  • Execute Instructions for Up to 232 Clock Cycles
  • Each Device Includes Four Bidirectional Event Pins for Additional Test Capability
  • Inputs Are TTL-Voltage Compatible
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • Packaged in 44-Pin Plastic Leaded Chip Carrier (FN), 68-Pin Ceramic Pin Grid Array (GB), and 68-Pin Ceramic Quad Flat Packages (HV)

    SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

Description

The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETM integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices.

The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals).

While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters.

The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs.

Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations.

Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer.

 

The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C.

 

 

 

 

 

NC - No internal connection

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)DSCC #Price | QuantityPackage | PinsPackage QTY | Package CarrierFootprintsSamples
5962-9322801MXAACTIVE-55 to 125 215.92 | 1kuCFP (HV) | 68 1 | TUBE Purchase Samples
5962-9322801MYAACTIVE-55 to 125 215.92 | 1kuCPGA (GB) | 68 1 | JEDEC TRAY (5+1) Download CAD Format for this FootprintPurchase Samples
SNJ54ACT8990GBACTIVE-55 to 1255962-9322801MYA215.92 | 1kuCPGA (GB) | 68 1 | JEDEC TRAY (5+1) Download CAD Format for this FootprintContact TI Distributor or Sales Office
SNJ54ACT8990HVACTIVE-55 to 1255962-9322801MXA215.92 | 1kuCFP (HV) | 68 1 | TUBE Contact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 11:22 AM GMT, 08 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 8 Weeks5962-9322801MXA
None Reported
View Distributors
TI Lead Time*: 8 Weeks5962-9322801MYA
None Reported
View Distributors
TI Lead Time*: 8 WeeksSNJ54ACT8990GB
None Reported
View Distributors
TI Lead Time*: 8 WeeksSNJ54ACT8990HV
EuropeEBV Elektronik 1
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
5962-9322801MXA  TBD POST-PLATE N/A for Pkg TypeViewView
5962-9322801MYA  TBD POST-PLATE N/A for Pkg TypeViewView
SNJ54ACT8990GB  TBD POST-PLATE N/A for Pkg TypeViewView
SNJ54ACT8990HV  TBD POST-PLATE N/A for Pkg TypeViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

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Technical Documents

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Datasheet

Application Notes

View Application Notes for Boundary Scan (JTAG) Support Devices

User Guides

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Tools & Software

NamePart # Company Tool / Software Type
Boundary-Scan Logic ModelsBSDLTexas InstrumentsSimulators
Scan EducatorSCAN_EDUCATORTexas InstrumentsSimulators

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