SN65LVDS302 Status: ACTIVE

Programmable 27-Bit Display Serial Interface Receiver

      
         
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Datasheet

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 SN65LVDS301 SN65LVDS302SN65LVDS303 SN65LVDS304 SN65LVDS305 SN65LVDS306 
Number of Parallel Outputs 27   27   27  
Number of Parallel Inputs27   27   27   
Data Throughput(MB/s)1755  1755  810  810  405  405  
Serial Data Receiver Channels 3   2   1  
Serial Data Transmitter Channels3   2   1   
Type of Line CircuitsubLVDS  subLVDS  subLVDS  subLVDS  subLVDS  subLVDS  
Supply Voltage(s)(V)1.8  1.8  1.8  1.8  1.8  1.8  
PLL Frequency(MHz)4 - 65  4 - 65  4 - 30  4 - 30  4 - 15  4 - 15  
FootprintSN65LVDS301  SN65LVDS302  SN65LVDS301  SN65LVDS302  SN65LVDS301  SN65LVDS302  
Operating Temp Range(Celsius)-40 to 85  -40 to 85  -40 to 85  -40 to 85  -40 to 85  -40 to 85  
Pin/Package80BGA MICROSTAR JUNIOR  80BGA MICROSTAR JUNIOR  80BGA MICROSTAR JUNIOR  80BGA MICROSTAR JUNIOR  80BGA MICROSTAR JUNIOR  80BGA MICROSTAR JUNIOR  
 SamplesSamplesSamplesSamplesSamplesSamples
 InventoryInventoryInventoryInventoryInventoryInventory

Customers Who Evaluated This Product Also Evaluated

  • SN65LVDS301: Programmable 27-Bit Display Serial Interface Transmitter
  • SN75LVDS84A: FlatLink(TM) Transmitter
  • TPS2041B: Single-Channel Current-Limited Power Distribution Switch
  • SN74HC14: Hex Schmitt-Trigger Inverters
  • LMV331: Single General Purpose Low-Voltage Comparator

Product Information

Features

  • Serial Interface Technology
  • Compatible with FlatLink™3G such as SN65LVDS301
  • Supports Video Interfaces up to 24-bit RGB Data and 3 Control Bits Received over 1, 2 or 3 SubLVDS Differential Lines
  • SubLVDS Differential Voltage Levels
  • Up to 1.755 Gbps Data Throughput
  • Three Operating Modes to Conserve Power
    • Active mode QVGA - 17 mW
    • Typical Shutdown - 0.7 µW
    • TypicalStandby Mode - 27 µW Typical
  • Bus-Swap Function for PCB-Layout Flexibility
  • ESD Rating > 4 kV (HBM)
  • Pixel Clock Range of 4 MHz-65 MHz
  • Failsafe on all CMOS Inputs
  • Packaged in 5 mm x 5 mm MicroStar Junior µBGA® with 0,5 mm Ball Pitch
  • Very low EMI meets SAE J1752/3 'Kh'-spec
  • APPLICATIONS
    • Small Low-Emission Interface between Graphics Controller and LCD Display
    • Mobile Phones & Smart Phones
    • Portable Multimedia Players

FlatLink is a trademark of Texas Instruments
µBGA is a trademark of Texas Instruments

Description

The SN65LVDS302 receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.

The serial data and clock are received via Sub Low-Voltage Differential Signalling (SubLVDS) lines. The SN65LVDS302 supports three operating power modes (Shutdown, Standby, and Active) to conserve power.

When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the Pixel clock PCLK generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with the PCLK and DE held low, while all other parallel outputs are pulled high.

The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher load designs.

Two Link Select lines LS0 and LS1 select whether 1, 2, or 3 serial links are used. The RXEN input may be used to put the SN65LVDS302 in a Shutdown mode. The SN65LVDS302 enters an active Standby mode if the common mode voltage of the CLK input becomes shifted to VDDLVDS (e.g., transmitter releases the CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS302 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with VDD=0 V. This feature allows signal powerup before VCC is stabilized.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierSymbolsFootprintsSamples
SN65LVDS302ZQEACTIVE-40 to 853.10 | 100uBGA MICROSTAR JUNIOR (ZQE) | 80 View 360 | JEDEC TRAY (5+1) Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
SN65LVDS302ZQERACTIVE-40 to 852.85 | 100uBGA MICROSTAR JUNIOR (ZQE) | 80 View 2500 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this Footprint

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
SN65LVDS302ZQEAs of 10:26 AM GMT, 03 Jul 2009As of 10:26 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 6 Weeks AmericasDigiKey 1
 Mouser Electronics 266
SN65LVDS302ZQERAs of 10:26 AM GMT, 03 Jul 2009As of 10:26 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 12 Weeks AmericasDigiKey 949
 AsiaWPI >1k
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** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
SN65LVDS302ZQE RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HRViewView
SN65LVDS302ZQER RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

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Datasheet

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