SN65LVDS304 Status: ACTIVE

Product Information

Features

• Serial Interface Technology
• Compatible With FlatLink3G Such as SN65LVDS303
• Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over 1 or 2 SubLVDS Differential Lines
• SubLVDS Differential Voltage Levels
• Up to 810-Mbps Data Throughput
• Three Operating Modes to Conserve Power
  • Active mode QVGA: 17 mW
  • Typical Shutdown: 0.7 µW
  • TypicalStandby Mode: 27 µW Typical
• Bus-Swap Function for PCB-Layout Flexibility
• ESD Rating > 4 kV (HBM)
• Pixel Clock Range of 4 MHz-30 MHz
• Failsafe on all CMOS Inputs
• Packaged in 5-mm × 5-mm MicroStar Junior µBGA® With 0,5-mm Ball Pitch
• Very Low EMI Meets SAE J1752/3 'Kh'-Spec
• APPLICATIONS
  • Small Low-Emission Interface Between Graphics Controller and LCD Display
  • Mobile Phones and Smart Phones
  • Portable Multimedia Players

FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.

Description

The SN65LVDS304 receiver deserializes FlatLink™3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS304 receiver contains one shift register to load 30 bits from 1 or 2 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the channel parity error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.

The serial data and clock are received via sub-low-voltage differential signalling (SubLVDS) lines. The SN65LVDS304 supports three operating power modes (shutdown, standby, and active) to conserve power.

When receiving, the PLL locks to the incoming clock CLK and generates an internal high-speed clock at the line rate of the data lines. The data is serially loaded into a shift register using the internal high-speed clock. The deserialized data is presented on the parallel output bus with a recreation of the pixel clock, PCLK, generated from the internal high-speed clock. If no input CLK signal is present, the output bus is held static with PCLK and DE held low, while all other parallel outputs are pulled high.

The parallel (CMOS) output bus offers a bus-swap feature. The SWAP control pin controls the output pin order of the output pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7], G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the LCD driver pinout or to put the receiver device on the top side or the bottom side of the PCB. The F/S control input selects between a slow CMOS bus output rise time for best EMI and power consumption and a fast CMOS output for increased speed or higher-load designs.

The link select line, LS, selects whether 1 or 2 serial links are used. The RXEN input can be used to put the SN65LVDS304 in a shutdown mode. The SN65LVDS304 enters an active standby mode if the common mode voltage of the CLK input becomes shifted to V_DDLVDS (e.g., transmitter releases CLK output into high-impedance). This minimizes power consumption without the need of switching an external control pin. The SN65LVDS304 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS and SubLVDS signals are 2-V tolerant with V_DD = 0 V. This feature allows signal powerup before V_CC is stabilized.