SN74ABT8996 Status: ACTIVE

10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers

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Datasheet

10-Bit Addressable Scan Ports Multi-Drop Addressable IEEE 1149.1 (Rev. C) (PDF 935 KB)
15 Apr 1999

	SN54ABT8996	SN74ABT8996
Voltage Nodes(V)	5	5
Vcc range(V)	4.5 to 5.5	4.5 to 5.5
Input Level	TTL	TTL
Output Level	TTL	TTL
Rating	Military	Catalog
Technology Family	JTAG	JTAG
	Samples	Samples
	Inventory	Inventory

Other qualified versions of SN74ABT8996

Version	Part Number	Definition
Military	SN54ABT8996	QML certified for Military and Defense Applications

Customers Who Evaluated This Product Also Evaluated

SN74ABT273: Octal Edge-Triggered D-Type Flip-Flops With Clear

SN74ABT827: 10-Bit Buffers/Drivers With 3-State Outputs

SN74ABT125: Quadruple Bus Buffer Gates With 3-State Outputs

Product Information

Features

Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
Extend Scan Access From Board Level to Higher Levels of System Integration
Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
10-Bit Address Space Provides for Up to 1021 User-Specified Board Addresses
Bypass (BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
Connect (CON\) Pin Provides Indication of Primary-to-Secondary Connection
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL) Support Backplane Interface at Primary and High Fanout at Secondary
Package Options Include Plastic Small- Outline (DW) and Thin Shrink Small- Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

SCOPE is a trademark of Texas Instruments Incorporated.

Description

The 'ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TI^TM) SCOPE^TM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPE^TM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Standard 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP.

View All Description in Datasheet

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
CABT8996DWRG4	ACTIVE	-40 to 85	7.15 \| 1ku	SOIC (DW) \| 24	View	2000 \| LARGE T&R	Purchase Samples
SN74ABT8996DW	ACTIVE	-40 to 85	7.15 \| 1ku	SOIC (DW) \| 24	View	25 \| TUBE	Purchase Samples
SN74ABT8996DWR	ACTIVE	-40 to 85	7.15 \| 1ku	SOIC (DW) \| 24	View	2000 \| LARGE T&R	Purchase Samples
SN74ABT8996PW	ACTIVE	-40 to 85	7.15 \| 1ku	TSSOP (PW) \| 24	View	60 \| TUBE	Purchase Samples
SN74ABT8996PWLE	OBSOLETE	-40 to 85		TSSOP (PW) \| 24	View		Not Available
SN74ABT8996PWR	ACTIVE	-40 to 85	7.15 \| 1ku	TSSOP (PW) \| 24	View	2000 \| LARGE T&R	Purchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:48 AM GMT, 09 Feb 2010
Region	Company	In Stock	Purchase
TI Lead Time*: 20 WeeksCABT8996DWRG4
None Reported View Distributors
TI Lead Time*: 16 WeeksSN74ABT8996DW
Americas	Rochester Electronics	>1k
Worldwide	Mouser Electronics	46
TI Lead Time*: 20 WeeksSN74ABT8996DWR
Americas	Rochester Electronics	>1k
TI Lead Time*: 18 WeeksSN74ABT8996PW
Americas	Rochester Electronics	>1k
Worldwide	DigiKey	Available
TI Lead Time*: 22 WeeksSN74ABT8996PWR
Americas	Rochester Electronics	>1k
Worldwide	DigiKey	>1k
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CABT8996DWRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ABT8996DW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ABT8996DWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ABT8996PW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ABT8996PWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74ABT8996

Datasheet

10-Bit Addressable Scan Ports Multi-Drop Addressable IEEE 1149.1 (Rev. C) (PDF, 935 KB)
15 Apr 1999

Application Notes

Testability Primer (Rev. D) (PDF, 360 KB) 9117 views
11 Mar 2005
Testability Primer (Rev. C) (PDF, 592 KB) 9117 views
01 Oct 1996
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 28292 views
24 May 2004 Read Abstract
Cascading Multiple Linking Addressable Scan Port Devices (HTM, 8 KB) 686 views
05 Nov 2002 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 23173 views
28 May 2003 Read Abstract
Programming CPLDs Via the 'LVT8986 LASP (HTM, 8 KB) 1268 views
01 Nov 2005 Read Abstract

View Application Notes for Boundary Scan (JTAG) Support Device

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 49573 views
16 Jan 2007
LASP Demo Board User's Guide (PDF, 1209 KB) 814 views
01 Nov 2005

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 16371 views
07 Oct 2003

Tools & Software

Name	Part #	Company	Tool / Software Type
Boundary-Scan Logic Models	BSDL	Texas Instruments	Simulators
Scan Educator	SCAN_EDUCATOR	Texas Instruments	Simulators

Customers Who Evaluated This Product Also Evaluated...
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SN74ABT827	10-Bit Buffers/Drivers With 3-State Outputs	BUFFER/DRIVER/TRANSCEIVER-NON-INVERTING BUFFER/DRIVER	TI customers also evaluated this product.
SN74ABT125	Quadruple Bus Buffer Gates With 3-State Outputs	BUFFER/DRIVER/TRANSCEIVER-NON-INVERTING BUFFER/DRIVER	TI customers also evaluated this product.
SN74ACT574	Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs	FLIP-FLOP/LATCH/REGISTER-D-TYPE(3-STATE)FLIP-FLOP	TI customers also evaluated this product.
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SN74ABT8996 Status: ACTIVE

10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers

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