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SN74ABT8996 Status: ACTIVE

10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers


      
         
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 SN54ABT8996 SN74ABT8996
Voltage Nodes(V)5  5  
Vcc range(V)4.5 to 5.5  4.5 to 5.5  
Input LevelTTL  TTL  
Output LevelTTL  TTL  
RatingMilitary  Catalog  
Technology FamilyJTAG  JTAG  
 SamplesSamples
 InventoryInventory

Other qualified versions of SN74ABT8996

Version Part Number Definition
Military SN54ABT8996 QML certified for Military and Defense Applications

Customers Who Evaluated This Product Also Evaluated

  • SN54ACT8990: Test Bus Controllers
  • SN74LVTH182646A: 3.3-V ABT Scan Test Devices With 18-Bit Transceivers And Registers
  • SN74LVT18512: 3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers

Product Information

Features

  • Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
  • Extend Scan Access From Board Level to Higher Levels of System Integration
  • Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
  • Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
  • Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
  • Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
  • Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
  • 10-Bit Address Space Provides for Up to 1021 User-Specified Board Addresses
  • Bypass (BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
  • Connect (CON\) Pin Provides Indication of Primary-to-Secondary Connection
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL) Support Backplane Interface at Primary and High Fanout at Secondary
  • Package Options Include Plastic Small- Outline (DW) and Thin Shrink Small- Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

SCOPE is a trademark of Texas Instruments Incorporated.

Description

The 'ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TITM) SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Standard 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.

Most operations of the ASP are synchronous to the primary test clock (PTCK) input. This PTCK signal always is buffered directly onto the secondary test clock (STCK) output.

Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. The PTRST\ signal is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously.

When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgement of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state.

In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgement and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgement.

The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a non-matching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states.

Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored.

Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high.

The SN54ABT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8996 is characterized for operation from -40°C to 85°C.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierFootprintsSamples
CABT8996DWRG4ACTIVE-40 to 857.15 | 1kuSOIC (DW) | 24 View 2000 | LARGE T&R Download CAD Format for this FootprintPurchase Samples
SN74ABT8996DWACTIVE-40 to 857.15 | 1kuSOIC (DW) | 24 View 25 | TUBE Download CAD Format for this FootprintPurchase Samples
SN74ABT8996DWRACTIVE-40 to 857.15 | 1kuSOIC (DW) | 24 View 2000 | LARGE T&R Download CAD Format for this FootprintPurchase Samples
SN74ABT8996PWACTIVE-40 to 857.15 | 1kuTSSOP (PW) | 24 View 60 | TUBE Download CAD Format for this FootprintPurchase Samples
SN74ABT8996PWLEOBSOLETE-40 to 85 TSSOP (PW) | 24 View   Download CAD Format for this FootprintNot Available
SN74ABT8996PWRACTIVE-40 to 857.15 | 1kuTSSOP (PW) | 24 View 2000 | LARGE T&R Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 11:05 AM GMT, 06 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 16 WeeksCABT8996DWRG4
None Reported
View Distributors
TI Lead Time*: 4 WeeksSN74ABT8996DW
AmericasRochester Electronics >1k
WorldwideMouser Electronics 46
TI Lead Time*: 16 WeeksSN74ABT8996DWR
AmericasRochester Electronics >1k
TI Lead Time*: 4 WeeksSN74ABT8996PW
AmericasRochester Electronics >1k
WorldwideDigiKey  Available
TI Lead Time*: 20 WeeksSN74ABT8996PWR
AmericasRochester Electronics >1k
WorldwideDigiKey >1k
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
CABT8996DWRG4 RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
SN74ABT8996DW RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
SN74ABT8996DWR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
SN74ABT8996PW RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView
SN74ABT8996PWR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIMViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74ABT8996 Help

Datasheet

Application Notes

View Application Notes for Boundary Scan (JTAG) Support Devices

User Guides

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Tools & Software

NamePart # Company Tool / Software Type
Boundary-Scan Logic ModelsBSDLTexas InstrumentsSimulators
Scan EducatorSCAN_EDUCATORTexas InstrumentsSimulators

Customers Who Evaluated This Product Also Evaluated...
Part # Name Product Family Comments
SN54ACT8990 Test Bus Controllers BOUNDARY SCAN (JTAG) LOGIC-BOUNDARY SCAN (JTAG) SUPPORT DEVICES TI customers also evaluated this product.
SN74LVTH182646A 3.3-V ABT Scan Test Devices With 18-Bit Transceivers And Registers BOUNDARY SCAN (JTAG) LOGIC-BOUNDARY SCAN (JTAG) BUS DEVICES TI customers also evaluated this product.
SN74LVT18512 3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers BOUNDARY SCAN (JTAG) LOGIC-BOUNDARY SCAN (JTAG) BUS DEVICES TI customers also evaluated this product.

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