SN74ACT8990 Status: ACTIVE

Test-Bus Controllers IEEE Std 1149.1 (JTAG) TAP Masters With 16-Bit Generic Host Interfaces

      
         
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Datasheet

Download - PDF Icon
  • Test Bus Controllers, JTAG TAP Masters With 16-Bit Generic Host Interfaces (Rev. E) (sn74act8990.pdf, 309 KB)
    01 Jan 1997 Download

 SN54ACT8990 SN74ACT8990
Voltage Nodes(V)5  5  
Vcc range(V)4.5 to 5.5  4.5 to 5.5  
Input LevelTTL  TTL  
Output LevelCMOS  CMOS  
RatingMilitary  Catalog  
Technology FamilyJTAG  JTAG  
 SamplesSamples
 InventoryInventory

Other qualified versions of SN74ACT8990

Version Part Number Definition
Military SN54ACT8990 QML certified for Military and Defense Applications

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  • Product Information

    Features

    • Members of the Texas Instruments SCOPETM Family of Testability Products
    • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
    • Control Operation of Up to Six Parallel Target Scan Paths
    • Accommodate Pipeline Delay to Target of Up to 31 Clock Cycles
    • Scan Data Up to 232 Clock Cycles
    • Execute Instructions for Up to 232 Clock Cycles
    • Each Device Includes Four Bidirectional Event Pins for Additional Test Capability
    • Inputs Are TTL-Voltage Compatible
    • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
    • Packaged in 44-Pin Plastic Leaded Chip Carrier (FN), 68-Pin Ceramic Pin Grid Array (GB), and 68-Pin Ceramic Quad Flat Packages (HV)

      SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

    Description

    The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETM integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices.

    The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals).

    While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters.

    The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs.

    Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations.

    Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer.

     

    The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C.

     

     

     

     

     

    NC - No internal connection

        

    Pricing / Packaging / CAD Design Tools / Samples

    PricePackagingCAD Design ToolsSamples
    DeviceStatusTemp (oC)Price | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierFootprintsSamples
    SN74ACT8990FNACTIVE-40 to 8525.74 | 1kuPLCC (FN) | 44 View 26 | TUBE Download CAD Format for this FootprintPurchase Samples
    SN74ACT8990FNRACTIVE-40 to 8525.74 | 1kuPLCC (FN) | 44 View 500 | LARGE T&R Download CAD Format for this FootprintPurchase Samples

    * Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

    Inventory

      TI Inventory Status Reported Distributor Inventory
    SN74ACT8990FNAs of 8:39 AM GMT, 05 Oct 2008As of 8:39 AM GMT, 05 Oct 2008
     In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
     94* 1274 | 20 Oct 4 Weeks AmericasArrow 221
     >10k | 7 Nov Mouser Electronics 26
      Rochester Electronics 59
      AsiaWPI 99
      EuropeAvnet-SILICA 4
    SN74ACT8990FNRAs of 8:39 AM GMT, 05 Oct 2008As of 8:39 AM GMT, 05 Oct 2008
     In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
     2500* >10k | 11 Nov 4 Weeks AmericasDigiKey 82
      Rochester Electronics 500
    View all Distributors  

    * Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

    ** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

    Quality & Lead (Pb)-Free Data

     Product ContentDPPM / MTBF / FIT Rate
    DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
    SN74ACT8990FN RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HRViewView
    SN74ACT8990FNR RoHS Compliant Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HRViewView

    * The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

    If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

    Technical Documents

    Datasheets

    • Test Bus Controllers, JTAG TAP Masters With 16-Bit Generic Host Interfaces (Rev. E) (sn74act8990.pdf, 309 KB)
      01 Jan 1997 Download

    Application Notes

    • Programming CPLDs Via the 'LVT8986 LASP (scea036.htm, 8 KB)
      01 Nov 2005 Abstract
    • Testability Primer (Rev. D) (ssya002d.pdf, 360 KB)
      11 Mar 2005 Download
    • Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm, 8 KB)
      24 May 2004 Abstract
    • Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (szza036b.htm, 8 KB)
      28 May 2003 Abstract
    • Cascading Multiple Linking Addressable Scan Port Devices (scta056.htm, 8 KB)
      05 Nov 2002 Abstract
    • Test-Bus Controller (scaa044.htm, 8 KB)
      31 Aug 2000 Abstract
    • Testability Primer (Rev. C) (ssya002c.pdf, 592 KB)
      01 Oct 1996 Download

    View Application Notes for Boundary Scan (JTAG) Support Devices

    User Guides

    • LOGIC Pocket Data Book (Rev. B) (scyd013b.pdf, 6001 KB)
      16 Jan 2007 Download
    • LASP Demo Board User's Guide (sceu001.pdf, 1209 KB)
      01 Nov 2005 Download

    More Literature

    • Logic Cross-Reference (Rev. A) (scyb017a.pdf, 2938 KB)
      07 Oct 2003 Download

    Tools & Software

    NamePart # Company Tool / Software Type
    Boundary-Scan Logic ModelsBSDLTexas InstrumentsSimulators
    Scan EducatorSCAN_EDUCATORTexas InstrumentsSimulators

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