SN74ACT8997 Status: ACTIVE

Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled TAP Concatenators

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Datasheet

Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled IEEE Std (Rev. D) (PDF 657 KB)
01 Dec 1996

	SN54ACT8997	SN74ACT8997
Voltage Nodes(V)	5	5
Vcc range(V)	4.5 to 5.5	4.5 to 5.5
Input Level	TTL	TTL
Output Level	CMOS	CMOS
Rating	Military	Catalog
Technology Family	JTAG	JTAG
	Samples	Samples
	Inventory	Inventory

Other qualified versions of SN74ACT8997

Version	Part Number	Definition
Military	SN54ACT8997	QML certified for Military and Defense Applications

Customers Who Evaluated This Product Also Evaluated

SN74ACT8990: Test-Bus Controllers IEEE Std 1149.1 (JTAG) TAP Masters With 16-Bit Generic Host Interfaces
SN54ACT8997: Scan Path Linkers With 4-Bit Identification Buses

Product Information

Features

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Serial Test Bus
Allow Partitioning of System Scan Paths
Can Be Cascaded Horizontally or Vertically
Select Up to Four Secondary Scan Paths to Be Included in a Primary Scan Path
Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals
Include 4-Bit Identification Bus for Scan-Path Identification
Inputs Are TTL Compatible
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

Description

The 'ACT8997 are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.

The 'ACT8997 enhance the scan capability of TI's SCOPE^TM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.

By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.

All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.

The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.

The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
CACT8997DWRG4	ACTIVE	0 to 70	7.15 \| 1ku	SOIC (DW) \| 28	View	1000 \| LARGE T&R	Purchase Samples
SN74ACT8997DW	ACTIVE	0 to 70	7.15 \| 1ku	SOIC (DW) \| 28	View	20 \| TUBE	Purchase Samples
SN74ACT8997DWR	ACTIVE	0 to 70	7.15 \| 1ku	SOIC (DW) \| 28	View	1000 \| LARGE T&R	Purchase Samples
SN74ACT8997NT	OBSOLETE	0 to 70		PDIP (NT) \| 28	View		Not Available

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 11:08 AM GMT, 08 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 16 WeeksCACT8997DWRG4
None Reported View Distributors
TI Lead Time*: 4 WeeksSN74ACT8997DW
Americas	Arrow	71
	Avnet	507
	Rochester Electronics	1k
Asia	WPI	200
Europe	Avnet-SILICA	20
Europe	EBV Elektronik	19
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	20
TI Lead Time*: 16 WeeksSN74ACT8997DWR
Americas	Rochester Electronics	>1k
Worldwide	DigiKey	920
Call**SN74ACT8997NT
Americas	Rochester Electronics	>1k
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
CACT8997DWRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ACT8997DW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74ACT8997DWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74ACT8997

Datasheet

Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled IEEE Std (Rev. D) (PDF, 657 KB)
01 Dec 1996

Application Notes

Testability Primer (Rev. D) (PDF, 360 KB) 8999 views
11 Mar 2005
Testability Primer (Rev. C) (PDF, 592 KB) 8999 views
01 Oct 1996
Shelf-Life Evaluation of Lead-Free Component Finishes (HTM, 8 KB) 26969 views
24 May 2004 Read Abstract
Cascading Multiple Linking Addressable Scan Port Devices (HTM, 8 KB) 660 views
05 Nov 2002 Read Abstract
Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (HTM, 8 KB) 21380 views
28 May 2003 Read Abstract
Programming CPLDs Via the 'LVT8986 LASP (HTM, 8 KB) 1212 views
01 Nov 2005 Read Abstract

View Application Notes for Boundary Scan (JTAG) Support Devices

User Guides

LOGIC Pocket Data Book (Rev. B) (PDF, 6001 KB) 46833 views
16 Jan 2007
LASP Demo Board User's Guide (PDF, 1209 KB) 745 views
01 Nov 2005

More Literature

Logic Cross-Reference (Rev. A) (PDF, 2938 KB) 15250 views
07 Oct 2003

Tools & Software

Name	Part #	Company	Tool / Software Type
Boundary-Scan Logic Models	BSDL	Texas Instruments	Simulators
Scan Educator	SCAN_EDUCATOR	Texas Instruments	Simulators

Simulation Models

BSDL Model
- BSDL Model of SN74ACT8997 (open-drain) (ZIP, 2 KB) 202 views
  06 Dec 2000
- BSDL Model of SN74ACT8997 (three-state) (ZIP, 2 KB) 215 views
  06 Dec 2000
IBIS Model
- SN74ACT8997 IBIS Model (Multiple File Format) 175 views
  03 Jun 1999 Read Abstract

Customers Who Evaluated This Product Also Evaluated...
Part #	Name	Product Family	Comments
SN74ACT8990	Test-Bus Controllers IEEE Std 1149.1 (JTAG) TAP Masters With 16-Bit Generic Host Interfaces	BOUNDARY SCAN (JTAG) LOGIC-BOUNDARY SCAN (JTAG) SUPPORT DEVICES	TI customers also evaluated this product.
SN54ACT8997	Scan Path Linkers With 4-Bit Identification Buses	BOUNDARY SCAN (JTAG) LOGIC-BOUNDARY SCAN (JTAG) SUPPORT DEVICES	TI customers also evaluated this product.

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SN74ACT8997 Status: ACTIVE

Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled TAP Concatenators

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