QML certified for Military and Defense Applications
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CD74HC74: High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
SN74HC74: Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
TLV1117-33: Single Output LDO, 800mA, Fixed(3.3), Internal Current limit, Thermal Overload Protection
Product Information
Features
Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
description/ordering information
The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
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Inventory
Reported Distributor Inventory as of 11:03 AM GMT, 26 Nov 2009
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