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SN74LS297 Status:ACTIVE

Digital Phase-Locked-Loop Filters

      
         
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The 'LS297 can perform the classic first-order phase-locked loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the divide-by-N modulos will determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D Clock /2N(Hz).

 

Datasheet

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  • Digital Phase-Locked-Loop Filters (sn74ls297.pdf, 543 KB)
    01 Mar 1988 Download

 SN74LS297
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Product Information

Features

  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher Order Loops
  • Useful Frequency from DC to:
    • 50 MHz Typical (K Clock)
    • 35 MHz Typical (I/D Clock)

 

Description

The SN54LS297 and SN74LS297 devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first order phase-locked loops as described in Figure 1.

Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and D are all programmed high, the K counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A through D inputs can maximize the overall performance of the digital phase-locked loop.

FIGURE 1-SIMPLIFIED BLOCK DIAGRAM
    

Pricing / Packaging / CAD Design Tools / Samples

Price ($US)PackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price ($US) | QuantityPackage | PinsTop Side MarkingPackage QTY | Package CarrierFootprintsSamples
SN74LS297NACTIVE0 to 7021.14 | 1kuPDIP (N) | 16 View 25 | TUBE Download CAD Format for this FootprintPurchase Samples
SN74LS297NE4ACTIVE0 to 7021.14 | 1kuPDIP (N) | 16 View 25 | TUBE Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
SN74LS297NAs of 8:19 AM GMT, 29 Aug 2008As of 8:19 AM GMT, 29 Aug 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* >10k | 3 Nov 8 Weeks AmericasRochester Electronics >1k
SN74LS297NE4As of 8:19 AM GMT, 29 Aug 2008As of 8:19 AM GMT, 29 Aug 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* >10k | 3 Nov 8 Weeks None Reported
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* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
SN74LS297N RoHS Compliant Pb-Free (RoHS) CU NIPDAU N/A for Pkg TypeViewView
SN74LS297NE4 RoHS Compliant Pb-Free (RoHS) CU NIPDAU N/A for Pkg TypeViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Datasheets

  • Digital Phase-Locked-Loop Filters (sn74ls297.pdf, 543 KB)
    01 Mar 1988 Download

Application Notes

  • Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm, 8 KB)
    24 May 2004 Abstract
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (szza036b.htm, 8 KB)
    28 May 2003 Abstract
  • TI IBIS File Creation, Validation, and Distribution Processes (szza034.htm, 9 KB)
    29 Aug 2002 Abstract
  • Designing With Logic (Rev. C) (sdya009c.htm, 8 KB)
    01 Jun 1997 Abstract
  • Digital PLL Design Using the SN54/74LS297 (Rev. B) (sdla005b.htm, 8 KB)
    01 Mar 1997 Abstract
  • Designing with the SN54/74LS123 (Rev. A) (sdla006a.htm, 9 KB)
    01 Mar 1997 Abstract
  • Live Insertion (sdya012.htm, 8 KB)
    01 Oct 1996 Abstract
  • Input and Output Characteristics of Digital Integrated Circuits (sdya010.htm, 9 KB)
    01 Oct 1996 Abstract

View Application Notes for Phase-Locked-Loops (PLLs) and Oscillators

User Guides

  • LOGIC Pocket Data Book (Rev. B) (scyd013b.pdf, 6001 KB)
    16 Jan 2007 Download

More Literature

  • Logic Selection Guide 2007 (Rev. Z) (sdyu001z.pdf, 2862 KB)
    24 Apr 2007 Download
  • Military Semiconductors Selection Guide 2004-2005 (Rev. D) (sgyc003d.pdf, 964 KB)
    10 Aug 2004 Download
  • Logic Cross-Reference (Rev. A) (scyb017a.pdf, 2938 KB)
    07 Oct 2003 Download
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CD74HC4046AHigh Speed CMOS Logic Phase-Locked-Loop with VCOTI customers also evaluated this product.

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