SN74LVC125A-EP Status: ACTIVE

Enhanced Product Quadruple Bus Buffer Gate With 3-State Outputs

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Datasheet

SN74LVC125A-EP (Rev. C) (PDF 349 KB)
12 Dec 2006

	SN74LVC125A-EP
Voltage Nodes(V)	3.3, 2.7, 2.5, 1.8
Vcc range(V)	1.65 to 3.6
Logic	True
Input Level	TTL/CMOS
Output Level	LVTTL
Output Drive(mA)	-24/24
No. of Outputs	4
tpd max(ns)	4.8
Static Current	0.01
Rating	HiRel Enhanced Product
Technology Family	LVC
	Samples
	Inventory

Other qualified versions of SN74LVC125A-EP

Version	Part Number	Definition
Automotive	SN74LVC125A-Q1	Q100 devices qualified for high-reliability automotive applications targeting zero defects
Catalog	SN74LVC125A	TI's standard catalog product

Customers Who Evaluated This Product Also Evaluated

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CD74HC4050: High Speed CMOS Logic Hex Non-Inverting Buffers
SN74LVC1G125: Single Bus Buffer Gate With 3-State Outputs
SN74LVC2G126: Dual Bus Buffer Gate With 3-State Outputs

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Product Information

Features

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

⁽¹⁾ Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

Pricing / Packaging / CAD Design Tools / Samples

				Price	Packaging			CAD Design Tools	Samples
Device	Status	Temp (^oC)	DSCC #	Price \| Quantity	Package \| Pins	Top Side Marking	Package QTY \| Package Carrier	Footprints	Samples
SN74LVC125AIPWREP	ACTIVE	-40 to 85	V62/04656-01XE	0.25 \| 1ku	TSSOP (PW) \| 14	View	2000 \| LARGE T&R	Purchase Samples
SN74LVC125AMDREP	ACTIVE	-55 to 125	V62/04656-02YE	0.63 \| 1ku	SOIC (D) \| 14	View	2500 \| LARGE T&R	Contact TI Distributor or Sales Office
V62/04656-01XE	ACTIVE	-40 to 85		0.25 \| 1ku	TSSOP (PW) \| 14	View	2000 \| LARGE T&R	Purchase Samples
V62/04656-02YE	ACTIVE	-55 to 125		0.63 \| 1ku	SOIC (D) \| 14	View	2500 \| LARGE T&R	Contact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:59 AM GMT, 26 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 20 WeeksSN74LVC125AIPWREP
Americas	Avnet	>1k
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 16 WeeksSN74LVC125AMDREP
Worldwide	DigiKey	>1k
TI Lead Time*: 20 WeeksV62/04656-01XE
None Reported View Distributors
TI Lead Time*: 16 WeeksV62/04656-02YE
None Reported View Distributors
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
SN74LVC125AIPWREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC125AMDREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
V62/04656-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
V62/04656-02YE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

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Datasheet

SN74LVC125A-EP (Rev. C) (PDF, 349 KB)
12 Dec 2006

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Part #	Name	Product Family	Comments
SN74LVC125A	Quadruple Bus Buffer Gate With 3-State Outputs	BUFFERS, DRIVERS AND TRANSCEIVERS-NON-INVERTING BUFFERS AND DRIVERS	TI customers also evaluated this product.
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SN74LVC125A-EP Status: ACTIVE

Enhanced Product Quadruple Bus Buffer Gate With 3-State Outputs

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Datasheet

Other qualified versions of SN74LVC125A-EP

Customers Who Evaluated This Product Also Evaluated

Product Information

Features

DESCRIPTION/ORDERING INFORMATION

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

Solution Guides

More Literature

Support and Community

Customer Tags

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