SN74LVC2G74 Status: ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

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Datasheet

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. M) (PDF 550 KB)
09 Feb 2007

	SN74LVC2G74
No. of Gates	2
tpd max(ns)	4.4
Output Level	CMOS
Pin/Package	8DSBGA, 8SM8, 8US8
IOH(mA)	-32
IOL(mA)	32
Vcc min(V)	1.65
Vcc max(V)	5.5
Approx. Price (US$)	0.18 \| 1ku
Operating Temp Range(Celsius)	-40 to 85
Technology Family	LVC
Input Level	CMOS
ICC(uA)	10
Rating	Catalog
	Samples
	Inventory

Other qualified versions of SN74LVC2G74

Version	Part Number	Definition
Automotive	SN74LVC2G74-Q1	Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product	SN74LVC2G74-EP	Supports Defense, Aerospace and Medical Applications

Customers Who Evaluated This Product Also Evaluated

SN74AUC1G74: Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset
SN74LVC1G175: Single D-Type Flip-Flop with Asynchronous Clear
SN74LVC1G123: Single Retriggerable Monostable Multivibrator with Schmitt-Trigger Inputs
SN74LVC1G08: Single 2-Input Positive-AND Gate
SN74LVC1G07: Single Buffer/Driver With Open-Drain Output
SN74LVC1G14: Single Schmitt-Trigger Inverter

More Related Products

Product Information

Features

Available in the Texas Instruments NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.9 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments

DESCRIPTION/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Pricing / Packaging / CAD Design Tools / Samples

			Price	Packaging		CAD Design Tools	Samples
Device	Status	Temp (^oC)	Price \| Quantity	Package \| Pins	Package QTY \| Package Carrier	Footprints	Samples
SN74LVC2G74DCTR	ACTIVE	-40 to 85	0.18 \| 1ku	SM8 (DCT) \| 8	3000 \| LARGE T&R
SN74LVC2G74DCTRE4	ACTIVE	-40 to 85	0.18 \| 1ku	SM8 (DCT) \| 8	3000 \| LARGE T&R	Purchase Samples
SN74LVC2G74DCTRG4	ACTIVE	-40 to 85	0.18 \| 1ku	SM8 (DCT) \| 8	3000 \| LARGE T&R
SN74LVC2G74DCUR	ACTIVE	-40 to 85	0.18 \| 1ku	US8 (DCU) \| 8	3000 \| LARGE T&R
SN74LVC2G74DCURE4	ACTIVE	-40 to 85	0.18 \| 1ku	US8 (DCU) \| 8	3000 \| LARGE T&R
SN74LVC2G74DCURG4	ACTIVE	-40 to 85	0.18 \| 1ku	US8 (DCU) \| 8	3000 \| LARGE T&R
SN74LVC2G74DCUT	ACTIVE	-40 to 85	0.41 \| 1ku	US8 (DCU) \| 8	250 \| SMALL T&R	Purchase Samples
SN74LVC2G74DCUTE4	ACTIVE	-40 to 85	0.41 \| 1ku	US8 (DCU) \| 8	250 \| SMALL T&R	Purchase Samples
SN74LVC2G74DCUTG4	ACTIVE	-40 to 85	0.41 \| 1ku	US8 (DCU) \| 8	250 \| SMALL T&R	Purchase Samples
SN74LVC2G74YZPR	ACTIVE	-40 to 85	0.22 \| 1ku	DSBGA (YZP) \| 8	3000 \| LARGE T&R

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:45 AM GMT, 06 Nov 2009
Region	Company	In Stock	Purchase
TI Lead Time*: 15 WeeksSN74LVC2G74DCTR
Americas	Arrow	>1k
	Newark	>1k
	Rochester Electronics	>1k
Asia	Farnell Asia	>1k
Europe	Avnet-SILICA	>1k
Europe	Farnell	>1k
Worldwide	DigiKey	>1k
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 15 WeeksSN74LVC2G74DCTRE4
Americas	Avnet	>1k
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 15 WeeksSN74LVC2G74DCTRG4
Worldwide	DigiKey	Available
TI Lead Time*: 12 WeeksSN74LVC2G74DCUR
Americas	Arrow	>1k
	Avnet	>1k
	Newark	>1k
	Rochester Electronics	>1k
Asia	Farnell Asia	>1k
	WPI	>1k
	Wintech	>1k
Europe	EBV Elektronik	>1k
Europe	Farnell	>1k
Worldwide	DigiKey	>1k
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 12 WeeksSN74LVC2G74DCURE4
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 12 WeeksSN74LVC2G74DCURG4
Americas	Avnet	>1k
Americas	Rochester Electronics	>1k
Asia	Farnell Asia	140
Europe	Farnell	140
Worldwide	DigiKey	>1k
Worldwide	Mouser Electronics	>1k
TI Lead Time*: 8 WeeksSN74LVC2G74DCUT
Americas	Arrow	>1k
Americas	Newark	>1k
Asia	Farnell Asia	606
Asia	WPI	100
Europe	EBV Elektronik	125
	Farnell	487
	Spoerle	500
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	283
TI Lead Time*: 8 WeeksSN74LVC2G74DCUTE4
Worldwide	DigiKey	Available
Worldwide	Mouser Electronics	210
TI Lead Time*: 8 WeeksSN74LVC2G74DCUTG4
Worldwide	DigiKey	Available
TI Lead Time*: 18 WeeksSN74LVC2G74YZPR
Americas	Arrow	>1k
Worldwide	DigiKey	>1k
View all Distributors

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

	Product Content				DPPM / MTBF / FIT Rate
Device	Eco Plan*	Lead / Ball Finish	MSL Rating / Peak Reflow	Details	Details
SN74LVC2G74DCTR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCTRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCTRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCUR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCURE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCURG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCUT	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCUTE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74DCUTG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	View	View
SN74LVC2G74YZPR	Green (RoHS & no Sb/Br)	SNAGCU	Level-1-260C-UNLIM	View	View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74LVC2G74

Datasheet

Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. M) (PDF, 550 KB)
09 Feb 2007

Application Notes

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Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices (HTM, 9 KB) 633 views
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Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) (HTM, 8 KB) 2400 views
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CMOS Power Consumption and CPD Calculation (Rev. B) (HTM, 9 KB) 3127 views
01 Jun 1997 Read Abstract
LVC Characterization Information (HTM, 8 KB) 2367 views
01 Dec 1996 Read Abstract
Understanding Advanced Bus-Interface Products Design Guide (PDF, 253 KB) 4062 views
01 May 1996

User Guides

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16 Jan 2007
Signal Switch Data Book (Rev. A) (PDF, 18396 KB) 9486 views
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LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) (PDF, 13291 KB) 6695 views
18 Dec 2002

Selection Guides

Logic Guide 2009 (Rev. Z) (PDF, 4263 KB) 88336 views
23 Jul 2009

Solution Guides

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11 Feb 2008

More Literature

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10 Apr 2006
Design Summary for WCSP Little Logic (Rev. B) (PDF, 295 KB) 1804 views
04 Nov 2004
SN74LVC1G97 and SN74LVC1G98 Product Clip (Rev. A) (PDF, 253 KB) 1612 views
13 Jul 2004
Military Low Voltage Solutions (PDF, 103 KB) 765 views
04 Apr 2001
SN74LVC1G3157 and SNS74LVC2G53 SPDT Analog Switches (PDF, 65 KB) 2400 views
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13 Jun 2002
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27 Mar 2002
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01 Sep 1996 Read Abstract

Simulation Models

HSpice Model
- HSPICE MODEL OF SN74LVC2G74 (ZIP, 91 KB) 336 views
  06 Oct 2006
IBIS Model
- SN74LVC2G74 IBIS Model (Multiple File Format) 270 views
  24 Sep 2002 Read Abstract

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SN74LVC2G74 Status: ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Most Popular Links

Datasheet

Other qualified versions of SN74LVC2G74

Customers Who Evaluated This Product Also Evaluated

Product Information

Features

DESCRIPTION/ORDERING INFORMATION

Pricing / Packaging / CAD Design Tools / Samples

Inventory

Quality & Lead (Pb)-Free Data

Technical Documents

Datasheet

Application Notes

User Guides

Selection Guides

Solution Guides

More Literature

Simulation Models

Support and Community

Customer Tags

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