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SN74SSQE32882 Status: ACTIVE

JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test


      
         
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 SN74SSQE32882SN74SSQEA32882 
VCC(V)1.425 to 1.575  1.5, 1.35  
Operating Frequency Range(Min)(MHz)300  300  
Operating Frequency Range(Max)(MHz)670  810  
Absolute Jitter (cycle-to-cycle)(ps)40  40  
t(phase error)(Max)(ps)50   
Input LevelSSTL_15  SSTL_15  
No. of Outputs60  60  
Pin/Package176BGA  176BGA  
 SamplesSamples
 InventoryInventory

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Product Information

Features

  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs
  • Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption
  • 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs
  • 1.5-V CMOS Inputs
  • Checks Parity on Command and Address (CS-gated) Data Inputs
  • Supports LVCMOS Switching Levels on RESET Input
  • RESET Input:
    • Disables Differential Input Receivers
    • Resets All Registers
    • Forces All Outputs into Pre-defined States
  • Optimal Pinout for DDR3 DIMM PCB Layout
  • Supports Four Chip Selects
  • Single Register Backside Mount Support
  • APPLICATIONS
    • DDR3-Registered DIMMs up to DDR3-1333
    • Single-, Dual- and Quad-Rank RDIMM

All other trademarks are the property of their respective owners

DESCRIPTION/ORDERING INFORMATION

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V.

All inputs are 1.5-V, CMOS-compatible. All outputs are 1.5-V CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn, and DxODTn can each be driven with a different strength and skew to optimize signal integrity, compensate for different loading, and balance signal travel speed.

The SN74SSQE32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input.

First, when the QCSEN input pin is open or pulled high, the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This mode is the QuadCS disabled mode. Alternatively, when the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This mode is the QuadCS enabled mode.

When QCSEN is high or floating, the device also supports an operating mode that allows a single device to be mounted on the back side of a DIMM array. This device can then be configured to keep the input bus termination (IBT) feature enabled for all input signals independent of MIRROR. The SN74SSQE32882. operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low. This data can either be re-driven to the outputs or used to access internal control registers. Details are covered in the Function Tables (each flip-flop) with QCSEN = low.

Input bus data integrity is protected by a parity function. All address and command input signals are summed; the last bit of the sum is then compared to the parity signal delivered by the system at the PAR_IN input one clock cycle later. If these two values do not match, the device pulls the open drain output ERROUT low. The control signals (DCKE0, DCKE1, DODT0, DODT1, and DCS[n:0]) are not part of this computation.

The SN74SSQE32882 implements different power-saving mechanisms to reduce thermal power dissipation and to support system power-down states. Power consumption is further reduced by disabling unused outputs.

The package design is optimal for high-density DIMMs. By aligning input and output positions towards DIMM finger-signal ordering and SDRAM ballout, the device de-scrambles the DIMM traces and allows low crosstalk designs with low interconnect latency. Edge-controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsPackage QTY | Package CarrierSamples
SN74SSQE32882ZALRACTIVE0 to 855.90 | 1kuBGA (ZAL) | 176 1000 | LARGE T&RContact TI Distributor or Sales Office
SN74SSQE32882ZCJRACTIVE0 to 855.90 | 1kuBGA (ZCJ) | 176 1000 | LARGE T&RContact TI Distributor or Sales Office

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

Reported Distributor Inventory as of 10:52 AM GMT, 24 Nov 2009
RegionCompanyIn StockPurchase
TI Lead Time*: 20 WeeksSN74SSQE32882ZALR
AsiaWPI 900
WorldwideDigiKey 608
TI Lead Time*: 20 WeeksSN74SSQE32882ZCJR
AsiaWPI 1k
WorldwideDigiKey 100
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
SN74SSQE32882ZALR RoHS Compliant Green (RoHS & no Sb/Br) SNAGAU Level-3-260C-168 HRViewView
SN74SSQE32882ZCJR RoHS Compliant Green (RoHS & no Sb/Br) SNAGAU Level-3-260C-168 HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Most useful technical documents for SN74SSQE32882 Help

Datasheet

Application Notes

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