TL16PIR552 Status:ACTIVE

Product Information

Features

• Dual TL16C550C Universal Asynchronous Receiver/Transmitters (UARTs)
• IEEE 1284 Bidirectional Parallel Data (PD) Port
  • Compatible With Standard Centronics Parallel Interface
  • Support for Parallel Protocols: Extended Capability Port (ECP) and Enhanced Parallel Port (EPP)
  • Data Path 16-Byte FIFO Buffer
  • Direct Memory Access (DMA) Transfer
  • Decompression of Run Length Encoded Data in ECP Reverse Mode
  • Direct Connection to Printer, No External Transceiver is Needed
• Serial Ports Have Infrared Data Association (IrDA) Inputs and Outputs
  • 1200 bps to 115.2 kbps Data Rate
• 16-Byte FIFOs Reduce CPU Interrupts
• 12 mA Drive Current for All 1284 Control Terminals and Parallel Port Data Terminals
• Programmable Auto Flow Control on the UARTs
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud-Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ -1) and Generates an Internal 16× Clock
• Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
• On-Board Prescaler With Programmable Divisor Values From 0 to 33
• Independent Control of Transmit, Receive, Line Status, and Data-Set Interrupts on Each Channel
• Fully Programmable Serial-Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 1 1/2-, or 2-Stop Bit Generation
  • Baud Generation (DC to 1 Mbit Per Second)
• False Start-Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
  • Loopback Controls for Communications Link-Fault Isolation
  • Break, Parity, Overrun, and Framing Error Simulation
• Fully Prioritized Interrupt System Controls
• Modem-Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)
• Available in 80-Pin Quad Flatpack (QFP) Package

Description

The TL16PIR552 has a dual-channel universal asynchronous receiver/transmitter (UART). The UART is similar to the TL16C550C. The device serves two serial input/output ports simultaneously in microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual UART can be read by the CPU at any time during functional operation. The information obtained includes the type and condition of the transfer operation being performed and the error condition.

The receiver and transmitter FIFOs in the UARTs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through RTS\ output and CTS\ input signals.

The TL16PIR552 UART includes a programmable baud-rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16× clock for the receiver logic. The UART accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 us and a typical character time is 10 us (start bit, eight data bits, stop bit).

Each serial channel has a prescaler with programmable divisor values from 0 to 33. The serial ports also have a dedicated infrared serial data input (IRSIN0/1) and the serial data outputs multiplex between a RS-232-type serial output or an infrared serial data output. This is selected through an internal register bit and uses the same SOUT0/1 output terminals. The same UART circuit is used for the data path for the IrDA or the RS-232 operations. Channel 0 is powered up at IR0 and channel 1 is powered up during the RS-232 mode.

In addition to dual communication capabilities, the TL16PIR552 provides the user with an IEEE 1284 host side compatible, bidirectional, parallel data port. The parallel port operates in a compatible, FIFO, extended capability port (ECP) with RLE data decompression mode, and in a enhanced parallel port (EPP) mode. The default mode of operation is compatible with the Centronics printer port. The parallel port and the two serial ports provide IBM PC/AT^TM-compatible computers with a single device to serve a 3-port system.

IBM and PC/AT are trademarks of International Business Machines Corporation.