TLK2211 Status: ACTIVE

Product Information

Features

• 600 mbps to 1.3 Gigabits Per Second (Gbps) Serializer/Deserializer
• Low Power Consumption <450 mW Typical at 1.25 Gbps
• LVPECL Compatible Differential I/O on High Speed Interface
• Single Monolithic PLL Design
• Support For 10 Bit Interface
• Receiver Differential Input Thresholds 200 mV Minimum
• Industrial Temperature Range
  From -40°C to 85°C
• IEEE 802.3 Gigabit Ethernet Compliant
• Advanced 0.25 µm CMOS Technology
• No External Filter Capacitors Required
• Comprehensive Suite of Built-In Testability
• IEEE 1149.1 JTAG Support
• 3.3 V Supply Voltage for Lowest Power Operation
• 3.3 V Tolerant on LVTTL Inputs
• Hot Plug Protection
• 64 Pin VQFP With Thermally Enhanced Package (PowerPAD)
• APPLICATIONS
  • Gigabit Ethernet Switches and Routers
  • Fibre Channel Storage Systems

Description

The TLK2211 gigabit ethernet transceiver provide for ultrahigh-speed full-duplex point-to-point data transmissions. These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 Gigabit Ethernet specification. The TLK2211 supports data rates from 1.0 Gbps through 1.3 Gbps.

The primary application of this device is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2211 performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.

The TLK2211 supports a standard 10-bit interface (TBI). In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.

The TLK2211 provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudo random binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.

The TLK2211 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK2211 PowerPADs be soldered to the thermal land on the board.

The TLK2211 is characterized for operation from -40°C to 85°C.

The TLK2211 use a 3.3-V supply. The I/O section is 3.3-V compatible. With the 3.3-V supply the chipset is very power-efficient, dissipating less than 600 mW typical power when operating at 1.25 Gbps.

The TLK2211 is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in high-impedance state.