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TMS320C6418 Status: ACTIVE

Fixed-Point Digital Signal Processor

      
         
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Datasheet

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Functional Block Diagram


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 TMS320C6418-500TMS320C6418-600
CPU1 C64x  1 C64x  
Peak MMACS4000  4800  
Frequency(MHz)500  600  
On-Chip L1/SRAM32 KB  32 KB  
On-Chip L2/SRAM512 KB  512 KB  
EMIF1 32-Bit  1 32-Bit  
External Memory Type SupportedAsync SRAM,SDRAM,SBSRAM  Async SRAM,SDRAM,SBSRAM  
DMA64-Ch EDMA  64-Ch EDMA  
HPI1 32/16-Bit  1 32/16-Bit  
McBSP2  2  
I2C2  2  
McASP2  2  
Trace EnabledYes  Yes  
Timers3 32-Bit GP  3 32-Bit GP  
Hardware AcceleratorsVCP  VCP  
Core Supply (Volts)1.2 V  1.4 V  
IO Supply (Volts)3.3 V  3.3 V  
Operating Temperature Range (°C)-40 to 105  0 to 90  
 SamplesSamples
 InventoryInventory

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Product Information

Features

  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
    • Commercial Temperature Device
      • 1.67-ns Instruction Cycle Time
      • 600-MHz Clock Rate
      • 4800 MIPS
    • Extended Temperature Device
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • Viterbi Decoder Coprocessor (VCP)
    • Supports Over 500 7.95-Kbps AMR
    • Programmable Code Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 4M-Bit (512K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.4-V Internal (-600)
  • 3.3-V I/Os, 1.2-V Internal (A-500)

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

Description

The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the EDMA controller.

The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusPrice | QuantityPackage | PinsPackage QTY | Package CarrierSymbolsFootprintsSamples
TMS320C6418GTS600ACTIVE48.70 | 100uFCBGA (GTS) | 288 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320C6418GTSA500ACTIVE48.70 | 100uFCBGA (GTS) | 288 60  Purchase Samples
TMS320C6418ZTS600ACTIVE48.70 | 100uFCBGA (ZTS) | 288 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320C6418ZTSA500ACTIVE48.70 | 100uFCBGA (ZTS) | 288 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
TMS320C6418GTS600As of 8:59 AM GMT, 03 Jul 2009As of 8:59 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 8 Weeks AmericasArrow 6
 DigiKey 3
 Mouser Electronics 50
 AsiaWPI 70
TMS320C6418GTSA500As of 8:59 AM GMT, 03 Jul 2009As of 8:59 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 1 WeekNone Reported
View Distributors		   
TMS320C6418ZTS600As of 8:59 AM GMT, 03 Jul 2009As of 8:59 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 16 Weeks AmericasArrow 240
 DigiKey 81
 Mouser Electronics 38
 Newark 40
 AsiaWPI 69
 EuropeFarnell 53
TMS320C6418ZTSA500As of 8:59 AM GMT, 03 Jul 2009As of 8:59 AM GMT, 03 Jul 2009
 Lead TimeRegionCompanyIn StockPurchase
 4 Weeks AmericasArrow 50
 Mouser Electronics 1
 Rochester Electronics 1
 EuropeEBV Elektronik 30
View all Distributors  

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
TMS320C6418GTS600  TBD SNPB Level-4-220C-72 HRViewView
TMS320C6418GTSA500  TBD SNPB Level-4-220C-72 HRViewView
TMS320C6418ZTS600  Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HRViewView
TMS320C6418ZTSA500  Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

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Datasheet

Application Notes

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Simulation Models

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Errata

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Tools & Software

NamePart # Company Tool / Software Type
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
C6416 Test & Evaluation BoardTMDX3260C6416Texas InstrumentsDevelopment Boards/EVMs
C6416 Test Evaluation Board (TEB) bundled with CCS & 510PP+ EmulatorTMDX3260E6416Texas InstrumentsDevelopment Boards/EVMs
Network and Video Development KitTMDX3PNV6416STexas InstrumentsDevelopment Platforms
Video Security over IP (VSIP) (NTSC)TMDXVSK642Texas InstrumentsDevelopment Platforms
XDS510 Class EmulatorsXDS510Texas InstrumentsEmulators/Analyzers
XDS560 Trace EmulatorXDS560TRACETexas InstrumentsEmulators/Analyzers
Blackhawk™ LAN560 JTAG EmulatorBlackhawkEmulators/Analyzers
Blackhawk™ PCI560 JTAG Emulator for TI DSPsBlackhawkEmulators/Analyzers
Blackhawk™ USB560 JTAG EmulatorBlackhawkEmulators/Analyzers
Blackhawk™ USB560BP JTAG EmulatorBlackhawkEmulators/Analyzers
Blackhawk™ XDS560 Trace SystemBlackhawkEmulators/Analyzers
JTAGjet USB 2.0 Emulator for TMS320Signum SystemsEmulators/Analyzers
XDS510PP PLUS JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
XDS510USB JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
XDS510USB PLUS JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
Small Form Factor (SFF) Software Defined Radio (SDR) Development PlatformTMDSSFFSDRTexas InstrumentsHardware Reference Designs
TMS320C6000 Chip Support LibrarySPRC090 Texas Instruments Application Software 
TMS320C64x DSP LibrarySPRC092 Texas Instruments Signal Processing Libraries 
TMS320C62x/TMS320C64x FastRTS LibrarySPRC122 Texas Instruments Signal Processing Libraries 
TMS320C64x Image LibrarySPRC094 Texas Instruments Signal Processing Libraries 
C64x+DSPLIBSPRC265 Texas Instruments Signal Processing Libraries 
C64x+BEDSPLIBSPRC263 Texas Instruments Signal Processing Libraries 
Drivers/Platform Support Package (PSP)SUPPORTPKG Texas Instruments Drivers / IO / Control Software 

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