TMS320C6452 Status:ACTIVE

TMS320C6452 Digital Signal Processor

      
         
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Datasheet

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  • TMS320C6452 Digital Signal Processors (Rev. B) (tms320c6452.pdf, 1767 KB)
    30 Jun 2008 Download
  • TMS320C6452 Digital Signal Processor Silicon Errata (sprz279.pdf, 136 KB)
    30 Jun 2008 Download

 TMS320C6452-720TMS320C6452-900
CPU1 C64x+  1 C64x+  
Peak MMACS5760  7200  
Frequency(MHz)720  900  
On-Chip L1/SRAM32 KB  32 KB  
On-Chip L2/SRAM1408 KB  1408 KB  
EMIF1 16-Bit EMIFA,1 32-Bit DDR2 EMIF  1 16-Bit EMIFA,1 32-Bit DDR2 EMIF  
External Memory Type SupportedAsync SRAM,SBSRAM,DDR2SDRAM  Async SRAM,SBSRAM,DDR2SDRAM  
DMA64-Ch EDMA  64-Ch EDMA  
EMAC10/100/1000  10/100/1000  
PCI1 32-Bit [66/33 MHz]  1 32-Bit [66/33 MHz]  
HPI1 32/16-Bit  1 32/16-Bit  
McASP1  1  
SPI1  1  
TSIP2  2  
UART1  1  
I2C1  1  
VLYNQ1  1  
Trace EnabledYes  Yes  
Timers4 64-Bit GP  4 64-Bit GP  
Core Supply (Volts)1.2 V  1.2 V  
IO Supply (Volts)3.3 V, 1.8 V, 1.2 V  3.3 V, 1.8 V, 1.2 V  
Operating Temperature Range (°C)0 to 90  0 to 90  
 SamplesSamples
 Inventory Not AvailableInventory

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Product Information

Features

  • High-Performance Digital Signal Processor
    • 720, 900-MHz C64x+™ Clock Rate
    • 1.39, 1.11-ns Instruction Cycle Time
    • 5760, 7200 MIPS
    • Eight 32-Bit C64x+ Instructions/Cycle
    • Fully Software-Compatible With C64x/Debug
    • Commercial Temperature Ranges
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module
      • Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-bit Data)
    • 8-bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-bit (32K-byte) L1P Program Cache [Direct Mapped]
    • 256K-bit (32K-byte) L1D Data Cache [2-Way Set-Associative]
    • L2 Unified Mapped RAM/Cache [Flexible Allocation]
      • 1408K-byte
  • Supports Little Endian Mode Only
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
    • Asynchronous 16-Bit Wide EMIF (EMIFA)
      • With up to 128M-Byte Total Address Reach
      • 64M-Byte Address Reach Per CE Space
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
    • Synchronous Memories (SBSRAM and ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 3-Port Gigabit Ethernet Switch Subsystem
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One UART (With RTS and CTS Flow Control)
  • One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Telecom Serial Interface Ports (TSIP0/1)
  • Multichannel Audio Serial Port (McASP)
    • Ten Serializers and SPDIF (DIT) Mode
  • 16/32-Bit Host-Port Interface (HPI)
  • Advanced Event Triggering (AET) Compatible
  • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
  • VLYNQ™ Interface (FPGA Interface)
  • On-Chip ROM Bootloader
  • Individual Power-Saving Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Package:
    • 529-pin nFBGA (ZUT suffix)
    • 19x19 mm 0.8 mm pitch BGA
    • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -900)

TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are trademarks of Texas Instruments.
I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.
All trademarks are the property of their respective owners.

Description

The TMS320C64x+™ DSPs (including the TMS320C6452 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6452 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including telecom infrastructure, imaging/medical, and communications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 7200 million instructions per second (MIPS) at a clock rate of 900 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate performance. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The device also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1408KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The device has a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; two telecom serial interface ports (TSIP); four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6452 device has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

    

Pricing / Packaging / CAD Design Tools / Samples

Price ($US)PackagingCAD Design ToolsSamples
DeviceStatusPrice ($US) | QuantityPackage | PinsPackage QTY | Package CarrierSymbolsFootprintsSamples
TMS320C6452ZUT9ACTIVE156.75 | 100uFCBGA (ZUT) | 529 84  Purchase Samples
TMX320C6452ZUT9ACTIVE188.30 | 100uFCBGA (ZUT) | 529   Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
TMS320C6452ZUT9As of 7:56 AM GMT, 07 Sep 2008As of 7:56 AM GMT, 07 Sep 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasAvnet 60
  Mouser Electronics 84
View all Distributors  

* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
TMS320C6452ZUT9  Pb-Free (RoHS Exempt) SNAGCU Level-4-245C-72HRViewView
TMX320C6452ZUT9      View

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Datasheets

  • TMS320C6452 Digital Signal Processors (Rev. B) (tms320c6452.pdf, 1767 KB)
    30 Jun 2008 Download
  • TMS320C6452 Digital Signal Processor Silicon Errata (sprz279.pdf, 136 KB)
    30 Jun 2008 Download

Application Notes

  • TMS320C6452 Power Consumption Summary (spraav3.htm, 8 KB)
    30 May 2008 Abstract
  • Implementing DDR2 PCB Layout on the TMS320C6452 DMSoC (Rev. A) (spraal0a.htm, 9 KB)
    25 Mar 2008 Abstract
  • EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (spraap4.htm, 8 KB)
    11 Dec 2007 Abstract
  • nFBGA Packaging Application Report (spraa99.htm, 8 KB)
    13 Mar 2007 Abstract

View Application Notes for TMS320C645x DSPs

User Guides

  • TMS320C6452/6451 DSP Subsystem User's Guide (Rev. A) (sprufb1a.htm, 8 KB)
    08 Aug 2008 Abstract
  • TMS320C6452/6451 Telecom Serial Interface Port (TSIP) User's Guide (Rev. A) (spruf96a.pdf, 483 KB)
    30 Jun 2008 Download
  • TMS320C6452/6451 Host Port Interface (HPI) User's Guide (Rev. A) (spruf87a.htm, 8 KB)
    30 May 2008 Abstract
  • TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide (spruf97.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 General Purpose Input/Output (GPIO) User's Guide (spruf95.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 Inter-Integrated Circuit (I2C) Module User's Guide (spruf94.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 Universal Asynchronous Receiver/Transmitter (UART) User's Guide (spruf93.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 Serial Port Interface (SPI) User's Guide (spruf92.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 Multichannel Audio Serial Port (McASP) User's Guide (spruf91.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 64-Bit Timer User's Guide (spruf90.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 VLYNQ Port User's Guide (spruf89.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 Peripheral Component Interconnect (PCI) User's Guide (spruf86.htm, 8 KB)
    02 Oct 2007 Abstract
  • TMS320C6452 DDR2 Memory Controller User's Guide (spruf85.htm, 8 KB)
    01 Oct 2007 Abstract

View User Guides for TMS320C645x DSPs

White Papers

View White Papers for TMS320C645x DSPs

More Literature

View More Literature for TMS320C645x DSPs

Tools & Software

NamePart # Company Tool / Software Type
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
C6452 DSP Evaluation ModuleTMDXEVM6452Texas InstrumentsDevelopment Boards/EVMs
C6455 Evaluation ModuleTMDXEVM6455Texas InstrumentsDevelopment Boards/EVMs
XDS510 Class EmulatorsXDS510Texas InstrumentsEmulators/Analyzers
XDS560 Trace EmulatorXDS560TRACETexas InstrumentsEmulators/Analyzers
TMS320C6455 DSP Starter Kit (DSK)TMDSDSK6455Texas InstrumentsStarter Kits
C64x+IMGLIB Simulink BlocksSPRC589 Texas Instruments Application-Specific Libraries 
C64x+IMGLIBSPRC264 Texas Instruments Signal Processing Libraries 
Chip Support Library for 6455SPRC234 Texas Instruments Drivers / IO / Control Software 
Network Developer's Kit (NDK) TCP/IP StackTMDSNDK Texas Instruments Drivers / IO / Control Software 
eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDMTMDXDAISXDM Texas Instruments Algorithms / Codecs 
C64x+IQMathLibrary Simulink BlocksSPRC590 Texas Instruments Application-Specific Libraries 

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