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TMS320DM641 Status: ACTIVE

Video/Imaging Fixed-Point Digital Signal Processor

      
         
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Datasheet

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  • TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors (Rev. E) (tms320dm641.pdf, 2532 KB)
    14 Oct 2005 Download
  • TMS320DM641, TMS320DM640 DSPs Silicon Errata (Silicon Revisions 2.0,1.2,1.1,1.0) (Rev. G) (sprz201g.pdf, 228 KB)
    31 Aug 2005 Download
  • TMS320DM640/1 Hardware Designer's Resource Guide (Rev. A) (spraa50a.htm, 8 KB)
    24 Oct 2005 Abstract


 TMS320DM641-500TMS320DM641-600
CPU1 C64x; Video  1 C64x; Video  
Peak MMACS4000  4800  
Frequency(MHz)500  600  
On-Chip L1/SRAM32 KB  32 KB  
On-Chip L2/SRAM128 KB  128 KB  
EMIF1 32-Bit  1 32-Bit  
External Memory Type SupportedAsync SRAM,SDRAM,SBSRAM  Async SRAM,SDRAM,SBSRAM  
DMA64-Ch EDMA  64-Ch EDMA  
Video Port (Configurable)2 8-Bit Single-Ch  2 8-Bit Single-Ch  
VIC1  1  
EMAC10/100  10/100  
HPI1 16-Bit  1 16-Bit  
McBSP2  2  
I2C1  1  
McASP1  1  
Trace EnabledYes  Yes  
Timers3 32-Bit GP  3 32-Bit GP  
Core Supply (Volts)1.2 V  1.4 V  
IO Supply (Volts)3.3 V  3.3 V  
Operating Temperature Range (°C)0 to 90  0 to 90  
 SamplesSamples
 Inventory Not AvailableInventory

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Product Information

Features

  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

Description

The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU–).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusPrice | QuantityPackage | PinsPackage QTY | Package CarrierSymbolsFootprintsSamples
TMS320DM641AGDK5ACTIVE30.70 | 100uFCBGA (GDK) | 548 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AGDK6ACTIVE33.75 | 100uFCBGA (GDK) | 548 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AGNZ5ACTIVE30.70 | 100uFCBGA (GNZ) | 548   Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AGNZ6ACTIVE33.75 | 100uFCBGA (GNZ) | 548 40 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AZDK6ACTIVE33.75 | 100uFCBGA (ZDK) | 548 60 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AZNZ5ACTIVE30.70 | 100uFCBGA (ZNZ) | 548 40 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641AZNZ6ACTIVE33.75 | 100uFCBGA (ZNZ) | 548 40 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM641GDK500OBSOLETE40.73 | 100uFCBGA (GDK) | 548   Download CAD Format for this Symbol Download CAD Format for this FootprintNot Available
TMS320DM641GDK600OBSOLETE44.35 | 100uFCBGA (GDK) | 548   Download CAD Format for this Symbol Download CAD Format for this FootprintNot Available
TMS320DM641GNZ500OBSOLETE40.73 | 100uFCBGA (GNZ) | 548   Download CAD Format for this Symbol Download CAD Format for this FootprintNot Available
TMS320DM641GNZ600ACTIVE44.35 | 100uFCBGA (GNZ) | 548   Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
TMS320DM641AGDK5As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 634* 3695 | 26 Nov 4 Weeks None Reported
View Distributors		   
 >10k | 3 Dec     
TMS320DM641AGDK6As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 4* 3695 | 28 Nov 6 Weeks None Reported
View Distributors		   
 >10k | 5 Dec     
TMS320DM641AGNZ5As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasRochester Electronics 15
TMS320DM641AGNZ6As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* >10k | 1 Dec 7 Weeks AmericasRochester Electronics 20
  EuropeEBV Elektronik 120
TMS320DM641AZDK6As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0* 3694 | 25 Nov 6 Weeks AmericasMouser Electronics 197
 >10k | 2 Dec Rochester Electronics 23
TMS320DM641AZNZ5As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 600* 15 | 16 Oct 4 Weeks None Reported
View Distributors		   
 >10k | 26 Nov     
TMS320DM641AZNZ6As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 10* 15 | 17 Oct 7 Weeks None Reported
View Distributors		   
 575 | 21 Nov     
 >10k | 1 Dec     
TMS320DM641GDK600As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasDigiKey 130
  Rochester Electronics 190
TMS320DM641GNZ500As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasRochester Electronics >1k
TMS320DM641GNZ600As of 8:13 AM GMT, 15 Oct 2008As of 8:13 AM GMT, 15 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 0*  Call**AmericasDigiKey 3
  Rochester Electronics 343
View all Distributors  

* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
TMS320DM641AGDK5  TBD SNPB Level-4-220C-72 HRViewView
TMS320DM641AGDK6  TBD SNPB Level-4-220C-72 HRViewView
TMS320DM641AGNZ6  TBD SNPB Level-4-220C-72 HRViewView
TMS320DM641AZDK6  Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HRViewView
TMS320DM641AZNZ5  Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HRViewView
TMS320DM641AZNZ6  Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Datasheets

  • TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors (Rev. E) (tms320dm641.pdf, 2532 KB)
    14 Oct 2005 Download
  • TMS320DM641, TMS320DM640 DSPs Silicon Errata (Silicon Revisions 2.0,1.2,1.1,1.0) (Rev. G) (sprz201g.pdf, 228 KB)
    31 Aug 2005 Download

Application Notes

  • TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) (spra433e.htm, 8 KB)
    04 Sep 2007 Abstract
  • Migrating from TMS320DM642/3/1/0 to the TMS320DM647/DM648 Device (spraam5.htm, 8 KB)
    07 Jun 2007 Abstract
  • Thermal Considerations for the DM64xx, DM64x, and C6000 Devices (spraal9.htm, 8 KB)
    20 May 2007 Abstract
  • TMS320DM640/1 Hardware Designer's Resource Guide (Rev. A) (spraa50a.htm, 8 KB)
    24 Oct 2005 Abstract
  • TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) (spraa84a.htm, 8 KB)
    20 Oct 2005 Abstract
  • TMS320DM64x Power Consumption Summary (Rev. F) (spra962f.htm, 9 KB)
    18 Feb 2005 Abstract
  • Use and Handling of Semiconductor Packages With ENIG Pad Finishes (spraa55.htm, 8 KB)
    31 Aug 2004 Abstract
  • Interfacing an LCD Controller to a DM642 Video Port (Rev. B) (spra975b.htm, 9 KB)
    03 May 2004 Abstract
  • High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A) (spra961a.htm, 9 KB)
    03 May 2004 Abstract
  • TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) (spra544d.htm, 8 KB)
    26 Apr 2004 Abstract
  • TMS320C6000 Board Design: Considerations for Debug (Rev. C) (spra523c.htm, 8 KB)
    21 Apr 2004 Abstract
  • TMS320C6000 McBSP Initialization (Rev. C) (spra488c.htm, 8 KB)
    08 Mar 2004 Abstract
  • TMS320C6000 EDMA IO Scheduling and Performance (spraa00.htm, 8 KB)
    05 Mar 2004 Abstract
  • Using IBIS Models for Timing Analysis (Rev. A) (spra839a.htm, 8 KB)
    15 Apr 2003 Abstract
  • TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) (spra511b.htm, 9 KB)
    04 Jun 2002 Abstract
  • TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) (spra537c.htm, 8 KB)
    17 Apr 2002 Abstract
  • TMS320C6000 Board Design for JTAG (Rev. C) (spra584c.htm, 8 KB)
    02 Apr 2002 Abstract
  • TMS320C6000 EMIF to External Flash Memory (Rev. A) (spra568a.htm, 8 KB)
    13 Feb 2002 Abstract
  • Cache Usage in High-Performance DSP Applications with the TMS320C64x (spra756.htm, 9 KB)
    13 Dec 2001 Abstract
  • Using a TMS320C6000 McBSP for Data Packing (Rev. A) (spra551a.htm, 9 KB)
    31 Oct 2001 Abstract
  • TMS320C6000 Enhanced DMA: Example Applications (Rev. A) (spra636a.htm, 9 KB)
    24 Oct 2001 Abstract
  • Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) (spra479a.htm, 8 KB)
    30 Sep 2001 Abstract
  • TMS320C6000 Host Port to MC68360 Interface (Rev. A) (spra545a.htm, 8 KB)
    30 Sep 2001 Abstract
  • Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) (spra455a.htm, 9 KB)
    31 Aug 2001 Abstract
  • TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) (spra541a.htm, 8 KB)
    31 Aug 2001 Abstract
  • TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) (spra542a.htm, 8 KB)
    31 Aug 2001 Abstract
  • TMS320C6000 System Clock Circuit Example (Rev. A) (spra430a.htm, 8 KB)
    15 Aug 2001 Abstract
  • TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) (spra489a.htm, 9 KB)
    23 Jul 2001 Abstract
  • TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) (spra528a.htm, 9 KB)
    10 Jul 2001 Abstract
  • TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) (spra487c.htm, 8 KB)
    30 Jun 2001 Abstract
  • TMS320C6000 Host Port to MPC860 Interface (Rev. A) (spra546a.htm, 8 KB)
    21 Jun 2001 Abstract
  • TMS320C6000 McBSP: IOM-2 Interface (Rev. A) (spra569a.htm, 8 KB)
    21 May 2001 Abstract
  • Circular Buffering on TMS320C6000 (Rev. A) (spra645a.htm, 8 KB)
    12 Sep 2000 Abstract
  • TMS320C6000 McBSP as a TDM Highway (Rev. A) (spra491a.htm, 9 KB)
    11 Sep 2000 Abstract
  • TMS320C6000 u-Law and a-Law Companding with Software or the McBSP (spra634.htm, 9 KB)
    02 Feb 2000 Abstract
  • General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point (spra619.htm, 8 KB)
    31 Jan 2000 Abstract
  • TMS320C6000 C Compiler: C Implementation of Intrinsics (spra616.htm, 8 KB)
    07 Dec 1999 Abstract
  • TMS320C6000 McBSP: I2S Interface (spra595.htm, 9 KB)
    08 Sep 1999 Abstract

View Application Notes for TMS320DM64x DSPs

User Guides

  • TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (Rev. J) (spru041j.htm, 8 KB)
    20 Mar 2008 Abstract
  • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. G) (spru732g.htm, 8 KB)
    20 Feb 2008 Abstract
  • TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. O) (spru190o.htm, 8 KB)
    03 Dec 2007 Abstract
  • TMS320C64x DSP Video Port/ VCXO Interpolated Control (VIC) Port Reference Guide (Rev. F) (spru629f.htm, 8 KB)
    15 Jun 2007 Abstract
  • TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) (spru266e.htm, 8 KB)
    11 Apr 2007 Abstract
  • TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) (spru175d.htm, 8 KB)
    26 Mar 2007 Abstract
  • TMS320C6000 DSP Multichannel Buffered Serial Port ( McBSP) Reference Guide (Rev. G) (spru580g.htm, 8 KB)
    14 Dec 2006 Abstract
  • TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) (spru234c.htm, 8 KB)
    15 Nov 2006 Abstract
  • TMS320C64x DSP Two Level Internal Memory Reference Guide (Rev. C) (spru610c.htm, 8 KB)
    28 Feb 2006 Abstract
  • TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) (spru578c.htm, 8 KB)
    01 Jan 2006 Abstract
  • TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) (spru728c.htm, 8 KB)
    01 Mar 2005 Abstract
  • TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) (spru582b.htm, 8 KB)
    25 Jan 2005 Abstract
  • TMS320C6000 Chip Support Library API Reference Guide (Rev. J) (spru401j.htm, 8 KB)
    13 Aug 2004 Abstract
  • TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) (spru628a.htm, 8 KB)
    26 Mar 2004 Abstract
  • TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) (spru584a.htm, 8 KB)
    25 Mar 2004 Abstract
  • TMS320C6000 DSP Designing for JTAG Emulation Reference Guide (spru641.htm, 8 KB)
    31 Jul 2003 Abstract
  • TMS320C6000 DSP Cache User's Guide (Rev. A) (spru656a.htm, 8 KB)
    05 May 2003 Abstract
  • TMS320C64x Technical Overview (Rev. B) (spru395b.htm, 8 KB)
    30 Jan 2001 Abstract

View User Guides for TMS320DM64x DSPs

Simulation Models

  • IBIS Model
    • DM641 GDK/GNZ IBIS Model (sprm125.ibs, 427 KB)
      05 Sep 2003 ibis
      • | zip
  • BSDL Model
    • DM641 GDK BSDL Model (sprm134.zip, 9 KB)
      12 Sep 2003 zip
    • DM641 GNZ BSDL Model (sprm131.zip, 9 KB)
      12 Sep 2003 zip