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TMS320DM6431 Status: ACTIVE

Digital Media Processor

      
         
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Datasheet

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  • TMS320DM6431 Digital Media Processor (Rev. C) (tms320dm6431.pdf, 2033 KB)
    06 Jun 2008 Download
  • TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. D) (sprz250d.pdf, 255 KB)
    14 Feb 2008 Download

 TMS320DM6431-300
CPU1 C64x+; DaVinci Video  
Peak MMACS2400  
Frequency(MHz)300  
On-Chip L1/SRAM64 KB  
On-Chip L2/SRAM64 KB  
ROM64 KB (Boot)  
EMIF1 8-Bit EMIFA,1 16-Bit DDR2  
External Memory Type SupportedAsync SRAM,DDR2 SDRAM,NAND Flash  
DMA64-Ch EDMA  
Video Port (Configurable)1 Dedicated Input  
EMAC10/100  
CAN1 HECC  
McBSP1  
I2C1  
UART1  
PWM3  
McASP1  
Timers2 64-Bit GP,1 64-Bit WD  
Core Supply (Volts)1.2 V  
IO Supply (Volts)1.8 V,3.3 V  
Operating Temperature Range (°C)0 to 90,-40 to 125  
 Samples
 Inventory

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Product Information

Features

  • High-Performance Digital Media Processor (DM6431)
    • 3.33-ns Instruction Cycle Time
    • 300-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 2400 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
      • C64x+ Instruction Set Features
        • Byte-Addressable (8-/16-/32-/64-Bit Data)
        • 8-Bit Overflow Protection
        • Bit-Field Extract, Set, Clear
        • Normalization, Saturation, Bit-Counting
        • VelociTI.2 Increased Orthogonality
        • C64x+ Extensions
          • Compact 16-bit Instructions
          • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (10-Bit) Interface
      • Glueless Interface to Common Video Decoders
  • External Memory Interfaces (EMIFs)
    • 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O)
      • Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • One UART With RTS and CTS Flow Control
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • One Multichannel Buffered Serial Port (McBSP0)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-3/-3Q/-3S)
  • Applications:
    • Digital Media
    • Networked Media Encode
    • Video Imaging

All trademarks are the property of their respective owners.

Description

The TMS320C64x+™ DSPs (including the TMS320DM6431 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6431 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1200 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6431 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6431 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of 32K-byte (KB) memory space that can be configured as mapped memory or direct mapped cache. The Level 1 data/memory memory/cache (L1D) consists of a 64KB memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 64KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6431 device includes a Video Processing Subsystem (VPSS) with a Video Processing Front-End (VPFE) input used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC). The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs).

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6431 and the network. The DM6431 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C port allows DM6431 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6431 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

    

Pricing / Packaging / CAD Design Tools / Samples

PricePackagingCAD Design ToolsSamples
DeviceStatusTemp (oC)Price | QuantityPackage | PinsPackage QTY | Package CarrierSymbolsFootprintsSamples
TMS320DM6431ZDU3ACTIVE0 to 9013.10 | 100uBGA (ZDU) | 376 60  Purchase Samples
TMS320DM6431ZWT3ACTIVE0 to 9013.10 | 100uNFBGA (ZWT) | 361 90 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples
TMS320DM6431ZWTQ3ACTIVE-40 to 12514.40 | 100uNFBGA (ZWT) | 361 90 Download CAD Format for this Symbol Download CAD Format for this FootprintPurchase Samples

* Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

Inventory

  TI Inventory Status Reported Distributor Inventory
TMS320DM6431ZDU3As of 8:08 AM GMT, 10 Oct 2008As of 8:08 AM GMT, 10 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 168* >10k | 28 Oct 8 Weeks AmericasMouser Electronics 240
TMS320DM6431ZWT3As of 8:08 AM GMT, 10 Oct 2008As of 8:08 AM GMT, 10 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 1322* 1 | 10 Nov 8 Weeks AmericasMouser Electronics 90
 >10k | 24 Nov EuropeAvnet-SILICA 70
TMS320DM6431ZWTQ3As of 8:08 AM GMT, 10 Oct 2008As of 8:08 AM GMT, 10 Oct 2008
 In StockIn Progress QTY | DateLead TimeRegionCompanyIn StockPurchase
 1157* 1 | 19 Nov 8 Weeks AmericasAvnet 35
 5562 | 3 Dec     
 4 | 9 Dec     
 5562 | 16 Dec     
View all Distributors  

* Our information is updated daily, so please check back with us soon if this does not meet your needs. You may also contact your TI Authorized Distributor , including those listed above, for real time stock information.

** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

Quality & Lead (Pb)-Free Data

 Product ContentDPPM / MTBF / FIT Rate
DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
TMS320DM6431ZDU3 RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HRViewView
TMS320DM6431ZWT3 RoHS Compliant Pb-Free (RoHS) SNAGCU Level-3-260C-168 HRViewView
TMS320DM6431ZWTQ3 RoHS Compliant Pb-Free (RoHS) SNAGCU Level-3-260C-168 HRViewView

* The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

Technical Documents

Datasheets

  • TMS320DM6431 Digital Media Processor (Rev. C) (tms320dm6431.pdf, 2033 KB)
    06 Jun 2008 Download
  • TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. D) (sprz250d.pdf, 255 KB)
    14 Feb 2008 Download

Application Notes

  • 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) (slta066.htm, 8 KB)
    09 Oct 2008 Abstract
  • 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO (slta065.htm, 8 KB)
    09 Oct 2008 Abstract
  • 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO (slta064.htm, 8 KB)
    09 Oct 2008 Abstract
  • 5Vin DM643x Power using DC/DC Controllers and LDO (slta063.htm, 8 KB)
    09 Oct 2008 Abstract
  • Understanding the Davinci Preview Engine (Rev. A) (spraak8a.htm, 9 KB)
    23 Jul 2008 Abstract
  • Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) (spraav0a.htm, 8 KB)
    17 Jul 2008 Abstract
  • TMS320DM643x Power Consumption Summary (Rev. B) (spraao6b.htm, 8 KB)
    27 Jun 2008 Abstract
  • Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) (spraal6a.htm, 9 KB)
    26 Jun 2008 Abstract
  • How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) (spraan4a.htm, 8 KB)
    16 Jun 2008 Abstract
  • Using the TMS320DM643x Bootloader (Rev. D) (spraag0d.htm, 8 KB)
    05 May 2008 Abstract
  • EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (spraap4.htm, 8 KB)
    11 Dec 2007 Abstract
  • How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) (spraap3a.htm, 9 KB)
    14 Nov 2007 Abstract
  • TMS320DM643x Pin Multiplexing Utility (spraan3.htm, 8 KB)
    06 Jul 2007 Abstract
  • Thermal Considerations for the DM64xx, DM64x, and C6000 Devices (spraal9.htm, 8 KB)
    20 May 2007 Abstract
  • DaVinci Technology Background and Specifications (Rev. A) (sprt401a.pdf, 108 KB)
    04 Jan 2007 Download
  • TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) (spraa84a.htm, 8 KB)
    20 Oct 2005 Abstract

View Application Notes for TMS320DM643x DSPs

User Guides

  • TMS320C64x+ DSP Megamodule Reference Guide (Rev. J) (spru871j.htm, 8 KB)
    06 Aug 2008 Abstract
  • TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. B) (spru991b.htm, 8 KB)
    25 Jun 2008 Abstract
  • TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) (spru187o.htm, 8 KB)
    15 May 2008 Abstract
  • TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) (spru186q.htm, 8 KB)
    15 May 2008 Abstract
  • TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) (spruf30a.htm, 8 KB)
    05 May 2008 Abstract
  • TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. A) (spru995a.htm, 8 KB)
    01 May 2008 Abstract
  • TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) (spru997a.htm, 8 KB)
    08 Apr 2008 Abstract
  • TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) (spru988b.htm, 8 KB)
    18 Mar 2008 Abstract
  • TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) (spru980d.htm, 8 KB)
    13 Mar 2008 Abstract
  • TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) (sprueb8b.htm, 8 KB)
    06 Mar 2008 Abstract
  • TMS320DM643x DMP Video Processing Front End (VPFE) User's Guide (Rev. A) (spru977a.htm, 8 KB)
    03 Mar 2008 Abstract
  • TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) (spru987a.htm, 8 KB)
    03 Mar 2008 Abstract
  • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. G) (spru732g.htm, 8 KB)
    20 Feb 2008 Abstract
  • TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) (spru978e.htm, 8 KB)
    05 Feb 2008 Abstract
  • TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. B) (spru986b.htm, 8 KB)
    01 Nov 2007 Abstract
  • TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) (spru943c.htm, 8 KB)
    17 Sep 2007 Abstract
  • TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) (spru983a.htm, 8 KB)
    25 Jun 2007 Abstract
  • TMS320DM643x DMP High-End CAN Controller (HECC) User's Guide (Rev. A) (spru981a.htm, 8 KB)
    15 May 2007 Abstract
  • TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. A) (spru984a.htm, 8 KB)
    01 May 2007 Abstract
  • TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. A) (spru941a.htm, 8 KB)
    25 Apr 2007 Abstract
  • TMS320DM643x DMP 64-Bit Timer User's Guide (spru989.htm, 8 KB)
    18 Dec 2006 Abstract
  • TMS320C64x+ DSP Cache User's Guide (Rev. A) (spru862a.htm, 8 KB)
    24 Oct 2006 Abstract
  • TMS320C6000 Programmer's Guide (Rev. I) (spru198i.htm, 9 KB)
    30 Mar 2006 Abstract
  • TMS320C64x+ DSP Big-Endian Library Programmer's Reference (spruec5.htm, 8 KB)
    10 Mar 2006 Abstract
  • TMS320C64x+ Image/Video Processing Library Programmer's Reference (sprueb9.htm, 8 KB)
    10 Mar 2006 Abstract

View User Guides for TMS320DM643x DSPs

Simulation Models

  • IBIS Model
    • DM6431 ZDU IBIS Model (Rev. A) (sprm237a.ibs, 844 KB)
      09 Sep 2008 ibis
      • | zip
    • DM6431 ZWT IBIS Model (Rev. A) (sprm236a.ibs, 844 KB)
      09 Sep 2008 ibis
      • | zip
  • BSDL Model
    • DM6431 ZDU BSDL Model (sprm225.zip, 10 KB)
      16 Jan 2007 zip
    • DM6431 ZWT BSDL Model (sprm224.zip, 9 KB)
      16 Jan 2007 zip

View Simulation Models for TMS320DM643x DSPs

White Papers

  • BDTi Analysis of TI Digital Video Evaluation Module Whitepaper  (spry095.pdf, 648 KB)
    12 Feb 2007  Download
  • Transforming Performance to Safety in Automotive Applications Whitepaper  (spry093.pdf, 114 KB)
    13 Nov 2006  Download

View White Papers for TMS320DM643x DSPs

More Literature

  • TMS320C6000 DSP TCP/IP Stack Software (Rev. C) (sprt356c.pdf, 126 KB)
    04 Apr 2007 Download
  • Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) (sprt412b.pdf, 182 KB)
    13 Feb 2007 Download
  • DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) (sprt378d.pdf, 948 KB)
    13 Feb 2007 Download

View More Literature for TMS320DM643x DSPs

Tools & Software

NamePart # Company Tool / Software Type
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
DM6446 Digital Video Evaluation ModuleTMDSEVM6446Texas InstrumentsDevelopment Boards/EVMs
DM6437 Digital Video Development PlatformTMDSVDP6437Texas InstrumentsDevelopment Platforms
XDS510 Class EmulatorsXDS510Texas InstrumentsEmulators/Analyzers
Blackhawk™ LAN560 JTAG EmulatorBlackhawkEmulators/Analyzers
Blackhawk™ PCI560 JTAG Emulator for TI DSPsBlackhawkEmulators/Analyzers
Blackhawk™ USB560 JTAG EmulatorBlackhawkEmulators/Analyzers
Blackhawk™ USB560BP JTAG EmulatorBlackhawkEmulators/Analyzers
JTAGjet USB 2.0 Emulator for TMS320Signum SystemsEmulators/Analyzers
XDS510PP PLUS JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
XDS510USB JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
XDS510USB PLUS JTAG EmulatorSpectrum Digital, Inc.Emulators/Analyzers
TMS320C62x/TMS320C64x FastRTS LibrarySPRC122 Texas Instruments Signal Processing Libraries 
C64x+IMGLIBSPRC264 Texas Instruments Signal Processing Libraries 
H.264 Video DecoderTMDH264D Texas Instruments Algorithms / Codecs 
C64x+ IQMath Library - A Virtual Floating Point EngineSPRC542 Texas Instruments Signal Processing Libraries 
Network Developer's Kit (NDK) TCP/IP StackTMDSNDK Texas Instruments Drivers / IO / Control Software 
MP3 Audio EncoderTMDMP3E Texas Instruments Algorithms / Codecs 
VirtualLogix™ VLX for Digital Multimedia VirtualLogix Operating Systems (OS/RTOS) 
eXpressDSP Algorithm Standard – xDAIS Developer’s Kit and xDMTMDXDAISXDM Texas Instruments Algorithms / Codecs 
Multimedia Framework Products (MFP) - Codec Engine and xDAIS Framework ComponentsTMDMFP Texas Instruments Framework Software 

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