TMS320UC5402 Status:ACTIVE

Product Information

Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
• Data Bus With a Bus-Holder Feature
• Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
• 4K x 16-Bit On-Chip ROM
• 16K x 16-Bit On-Chip Dual-Access RAM
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Block-Memory-Move Instructions for Efficient Program and Data Management
• Instructions With a 32-Bit-Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt
• On-Chip Peripherals
  • Software-Programmable Wait-State Generator and Programmable Bank Switching
  • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
  • Two Multichannel Buffered Serial Ports (McBSPs)
  • Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
  • Two 16-Bit Timers
  • Six-Channel Direct Memory Access (DMA) Controller
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
• CLKOUT Off Control to Disable CLKOUT
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
• 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS)
• 1.8-V Core Power Supply
• 1.8-V to 3.6-V I/O Power Supply Enables Operation With a Single 1.8-V Supply or with Dual Supplies
• Available in a 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
• Available in a 144-Ball MicroStar™ Ball Grid Array (BGA) (GGU Suffix)

NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

Description

The TMS320UC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5402 unless otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.

Texas Instrument (TI) DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long-term reliability of the device.

System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to, the I/O buffers and powered down after the I/O buffers.

The UC5402 is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.