TMS470R1VF478 Status: ACTIVE

Product Information

Features

• High-Performance Static CMOS Technology
• TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
  • 24-MHz System Clock (60-MHz Pipeline Mode)
  • Independent 16/32-Bit Instruction Set
  • Open Architecture With Third-Party Support
  • Built-In Debug Module
  • Utilizes Big-Endian Format
• Integrated Memory
  • 288K-Byte Program Flash
    • One 32K-Byte Bank With Four 8K-Byte Sectors
    • One 256K-Byte Bank With Four 64K-Byte Sectors
    • Internal State Machine for Program and Erase
  • 16K-Byte Static RAM (SRAM)
• Operating Features
  • Core Supply Voltage (V_CC): 1.81 - 2.05 V
  • I/O Supply Voltage (V_CCIO): 3.0 - 3.6 V
  • Low-Power Modes: STANDBY and HALT
  • Industrial and Automotive Temperature Ranges
• 470+ System Module
  • 32-Bit Address Space Decoding
  • Bus Supervision for Memory and Peripherals
  • Analog Watchdog (AWD) Timer
  • Digital Watchdog (DWD) Timer
  • Real-Time Interrupt (RTI)
  • System Integrity and Failure Detection
• Direct Memory Access (DMA) Controller
  • 32 Control Packets and 16 Channels
• Frequency-Modulated Phase-Locked Loop (FMPLL)-Based Clock Module With Prescaler
  • Multiply-by-4 or -8 Internal FMPLL Option
• Six Communication Interfaces:
  • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
  • Serial Communications Interfaces (SCIs)
    • 2²⁴ Selectable Baud Rates
    • Asynchronous/Isosynchronous Modes
  • High-End CAN Controller
    • 32-Mailbox Capacity Each
    • Fully Compliant With CAN Protocol, Version 2.0B
  • Standard Can Controller (SCC)
    • 16-Mailbox Capacity
    • Fully Compliant With CAN Protocol, Version 2.0B
  • Multi-Buffered Serial Peripheral Interface (MibSPI)
    • 128-Word Buffer
    • Four DMA Channels
    • Six Chip Selects
• High-End Timer (HET)
  • 32 Programmable I/O Channels:
    • 30 High-Resolution Pins
    • 2 Standard-Resolution Pins
  • High-Resolution Share Feature (XOR)
  • High-End Timer RAM
    • 128-Instruction Capacity
• Two 10-Bit, 16-Channel Multi-Buffered ADCs
  • 128-Word FIFO Buffer
  • Single- or Continuous-Conversion Modes
  • 1.55 µs Minimum Sample and Conversion Time
  • Calibration Mode and Self-Test Features
• Four External Interrupts
• Flexible Interrupt Handling
• 3 Dedicated GIO Pins, 1 Input-Only GIO Pin, and 62 Additional Peripheral I/Os
• Compatible ROM Device (Planned)
• On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1⁽¹⁾ (JTAG) Test-Access Port
• 176-Pin Plastic Ball Grid Array (GJZ Suffix)
• Development System Support Tools Available
  • Code Composer Studio™ Integrated Development Environment (IDE)
  • HET Assembler and Simulator
  • Real-Time In-Circuit Emulation
  • Flash Programming
• External Clock Prescale (ECP) Module
  • Programmable Low-Frequency External Clock (CLK)

Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.

⁽¹⁾ The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.
⁽²⁾ Throughout the remainder of this document, the TMS470R1VF478 device name shall be referred to as TMS470R1VF478 or VF478.
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.
SAE Standard J1850 Class B Data Communication Network Interface

Description

The TMS470R1VF478⁽²⁾ device is a member of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The VF478 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF478 utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The VF478 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The VF478 devices contain the following:

• ARM7TDMI 16/32-Bit RISC CPU
• TMS470R1x system module (SYS) with 470+ enhancements [including a 16-channel direct-memory access (DMA) controller
• 288K-byte flash
• 16K-byte SRAM
• Frequency-modulated phase-locked loop (FMPLL) clock module
• Analog watchdog (AWD) timer
• Digital watchdog (DWD) timer
• Real-time interrupt (RTI) module
• Two serial peripheral interface (SPI) modules
• One serial communications interface (SCI) module
• High-end CAN controller (HECC)
• Standard CAN controller (SCC)
• Two 10-bit multi-buffered analog-to-digital converters (MibADC), 16-input channels
• Multi-buffered serial peripheral interface (MibSPI) module
• High-end timer (HET) controlling 32 I/Os
• External Clock Prescale (ECP) module
• Up to 65 I/O pins and 1 input-only pin

The functions performed by the 470+ system module (SYS) include: address decoding; memory protection; memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal interrupt sources; device clock control; and parallel signature analysis (PSA). This data sheet includes devicespecific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The VF478 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

The VF478 device has seven communication interfaces: a MibSPI, two SPIs, an HECC, an SCC, and an SCI. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to1 megabit per second (Mbps). The HECC is ideal for applications operating in harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g. automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length to be shifted into and out of the device at a programmed bit-transfer rate. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more information on the MibSPI peripheral, see the TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide (literature number SPNU217).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). The VF478 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The VF478 device has two 10-bit-resolution sample-and-hold MibADCs. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The frequency-modulated phase-locked loop (FMPLL) clock module contains a phase-locked loop, a clockmonitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the FMPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF478 device modules. For more detailed functional information on the FMPLL, see the TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221).