TNETE2201B

ACTIVE

1.25-gigabit Ethernet transceiver

Product details

Function SerDes Protocols LVPECL Supply voltage (V) 3.3 Signaling rate (MBits) 1000 Input signal LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) 0 to 70
Function SerDes Protocols LVPECL Supply voltage (V) 3.3 Signaling rate (MBits) 1000 Input signal LVTTL Output signal LVPECL Rating Catalog Operating temperature range (°C) 0 to 70
HTQFP (PHD) 64 256 mm² 16 x 16 HTQFP (PJD) 64 144 mm² 12 x 12 HTQFP (PJW) 64 166.41 mm² 12.9 x 12.9
  • 1.25 Gigabits Per Second (Gbps) Gigabit Ethernet Transceiver
  • Based on the P802.3Z Specification
  • Transmits Serial Data up to 1.25 Gbps
  • Operates With 3.3-V Supply Voltage
  • 5-V Tolerant on TTL Inputs
  • Interfaces to Electrical Cables/Backplane or Optical Modules
  • PECL Voltage Differential Signaling Load, 1 V Typ With 50
  • Receiver Differential Input Voltage 200 mV Minimum
  • Low Power Consumption
  • 64-Pin Quad Flat Pack With Thermally Enhanced Package

  • 1.25 Gigabits Per Second (Gbps) Gigabit Ethernet Transceiver
  • Based on the P802.3Z Specification
  • Transmits Serial Data up to 1.25 Gbps
  • Operates With 3.3-V Supply Voltage
  • 5-V Tolerant on TTL Inputs
  • Interfaces to Electrical Cables/Backplane or Optical Modules
  • PECL Voltage Differential Signaling Load, 1 V Typ With 50
  • Receiver Differential Input Voltage 200 mV Minimum
  • Low Power Consumption
  • 64-Pin Quad Flat Pack With Thermally Enhanced Package

The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by the P802.3z Gigabit Task Force.

The intended application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled-impedance media of approximately 50 . The transmission media can be printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in RBC clock rising edges.

The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.

The TNETE2201B provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TNETE2201B is characterized for operation from 0°C to 70°C.

The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by the P802.3z Gigabit Task Force.

The intended application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled-impedance media of approximately 50 . The transmission media can be printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in RBC clock rising edges.

The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.

The TNETE2201B provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TNETE2201B is characterized for operation from 0°C to 70°C.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet TNETE2201B: 1.25-Gigabit Ethernet Transceiver datasheet (Rev. D) 09 Aug 2007
White paper HDMP16x6A vs TNETE2201B 25 Jun 2003
Application note Interfacing Between LVPECL, VML, CML and LVDS Levels 17 Dec 2002
Application note Board Layout Adjustments Between the TNETE2201B and TLK2201 13 May 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
HTQFP (PHD) 64 View options
HTQFP (PJD) 64 View options
HTQFP (PJW) 64 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos