TSB12LV01B-EP Status: ACTIVE

Product Information

Features

• Link Core
  • Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus
  • Transmits and Receives Correctly Formatted 1394 Packets
  • Supports Asynchronous and Isochronous Data Transfers
  • Performs Function of 1394 Cycle Master
  • Generates and Checks 32-Bit CRC
  • Detects Lost Cycle-Start Messages
  • Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K Bytes
• Physical-Link Interface
  • Compatible With Texas Instruments Physical Layer Devices (PHYs)
  • Supports Transfer Speeds of 100, 200, and 400 Mbits/s
  • Timing Compliant with IEEE 1394a–2000
• Host Bus Interface
  • Provides Chip Control With Directly Addressable Registers
  • Is Interrupt Driven to Minimize Host Polling
  • Has a Generic 32-Bit Host Bus Interface
• General
  • Operates From a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs
  • Manufactured With Low-Power CMOS Technology
  • 100-Pin PZT Package for –40°C to 85°C (I Temperature) Operation
• Enhanced Plastic
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 85°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree

NOTE: Designing with this device may require extensive support. Before incorporating this device into a design, customers should contact TI or an Authorized TI Distributor.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).

The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below.

All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made:

• Two new internal registers have been added at CFR address 40h and 44h. The Host Bus Control Register at 40h and the Mux Control Register @44h are described in section 3.2.
• Three programmable general-purpose output pins have been added. A detailed description is provided in section 1.3.
• Several pin changes have been made. Refer to TSB12LV01A to TSB12LV01B Transition Document, TI literature number SLLA081 dated May 2000.

However, there are three restrictions that were not present in the TSB12LV01A device:

• The TSB12LV01B may only operate with a 50 MHz host-interface clock (BCLK) if the duty cycle is less than 5% away from the 50-50 point, (i.e., the duty cycle must be within 45-55% inclusive). A 40-60% duty cycle clock is acceptable for host clock frequencies at or below 47 MHz.
• The TSB12LV01B does not have bus holder cells on the PHY-link interface.
• As a result of removing the bus holder cells, the ISO\ pin (pin 69) was replaced with a Vcc pin on the TSB12LV01B.

This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus.