Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the 1394a-2000 Supplement
Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394
Fully Compliant With Open HCI Requirements
Provides Three 1394a-2000 Fully-Compliant Cable Ports at 100/200/400 Megabits Per Second (Mbits/s)
Full 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume
Extended Resume Signaling for Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down
Ultralow Power Sleep Mode
Node Power Class Information Signaling for System Power Management
Cable Power Presence Monitoring
Cable Ports Monitor Line Conditions for Active Connection to Remote Node.
Register Bits Provide Software Control of Contender Bit, Power Class Bits, Link Active Control Bit and 1394a-2000 Features
Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation
Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies
Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies
Low Cost 24.576-MHz Crystal Provides Transmit Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz
Separate Cable Bias (TPBIAS) for Each Port
Single 3.3-V Supply Operation
Low-Cost High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package
The TSB41AB3 provides the digital and analog transceiver functions required to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB3 is designed to interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41AB3 requires only an external 24.576-MHz crystal as a reference. An external clock may be used instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.
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Inventory
Reported Distributor Inventory as of 9:58 AM GMT, 20 Nov 2009
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