TSB41BA3B-EP Status: ACTIVE

Product Information

Features

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of -40°C to 110°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Fully Supports Provisions of IEEE 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (B Signifies 1394b Signaling)
• Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standards for High-Performance Serial Bus
• Fully Interoperable With Firewire™, DTVLink, SB1394, DishWire, and i.LINK™ Implementation of IEEE Std 1394
• Provides Three Fully Backward Compatible, (1394a-2000 Fully Compliant) Bilingual 1394b Cable Ports at 400 Megabits per Second (Mbps)
• Same Three Fully Backward Compatible Ports Are 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbps
• Full 1394a-2000 Support Includes:
  • Connection Debounce
  • Arbitrated Short Reset
  • Multispeed Concatenation
  • Arbitration Acceleration
  • Fly-By Concatenation
  • Port Disable/Suspend/Resume
  • Extended Resume Signaling for Compatibility With Legacy DV Devices
• Power-Down Features to Conserve Energy in Battery Powered Applications
• Low-Power Automotive Sleep Mode Support
• Fully Compliant With Open Host Controller Interface (OHCI) Requirements
• Cable Power Presence Monitoring
• Cable Ports Monitor Line Conditions for Active Connection to Remote Node
• Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a-2000 Features
• Data Interface to Link-Layer Controller Pin-Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz)
• Interface to Link-Layer Controller Supports Low-Cost Texas Instruments Bus-Holder Isolation
• Interoperable With Link-Layer Controllers Using 3.3-V Supplies
• Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies
• Low-Cost 49.152-MHz Crystal Provides Transmit and Receive Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz
• Separate Bias (TPBIAS) for Each Port
• Low-Cost, High-Performance, 80-Pin TQFP (PFP) Thermally Enhanced Package
• Software Device Reset (SWR)
• Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41BA3B-EP Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane
• 1394a-2000-Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise
• Cable/Transceiver Hardware Speed and Port Mode Are Selectable by Pin States
• Supports Connection to CAT5 Cable Transceiver by Allowing Ports to be Forced to Beta-Only S100 Mbps
• Supports Connection to S200 Plastic Optical Fiber Transceivers by Allowing Ports to be Forced to 1394b Beta-Only S200 Mbps and Beta-Only S100 Mbps
• Optical Signal Detect Input for All Ports in Beta Mode Enables Connection to Optical Transceivers
• Supports Use of 1394a Connectors by Allowing Ports 1 and 2 to Be Forced to 1394a-Only Mode

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.
FireWire is a trademark of Apple Computer, Inc. PowerPAD is a trademark of Texas Instruments.

Description

The TSB41BA3B-EP provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3B-EP interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.

The TSB41BA3B-EP is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.

The TSB41BA3B-EP may be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply to the PLLVDD-CORE and DVDD-CORE terminals must meet the requirements in the recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors, and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.

The TSB41BA3B-EP requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.