TSB43EA42 Status: ACTIVE

Product Information

Features

• 1394 Features
  • Integrated 400/200/100-Mbps 2-port/3-port PHY
  • Compliant with IEEE Std 1394-1995 and IEEE Std 1394a-2000
  • Supports bus manager functions and automatic 1394 self-id verification
  • Separate asynchronous acknowledgement (Ack) buffers decrease Ack-tracking burden on external CPU
• DTCP and AES Encryption Support for MPEG-DVB and DSS (TSB43EA42/43 and TSB43EC42/43 Only)
  • DTCP encryption support on 1394 bus
  • AES128 encryption support on HSDI path (TSB43EC42/43 only)
  • Support for up to two encrypted/decrypted streams at one time
  • Full or restricted AKE performed with hardware assist
  • Secure method for loading DTCP and AES128 information using Ex-CPU interface
  • Localization support compliant with DTCP draft revision 1.51.
• Video Interfaces
  • Two configurable high-speed data ports for video data
    • One port configurable as parallel or serial
    • One port serial only
  • Pass-through modes for HSDI0 and HSDI1
  • Packet Insertion - Two insertion buffers per HSDI for PAT, PMT, SIT, and DIT packets
  • PID filtering (32 PID filters per HSDI port)
• External CPU Interfaces
  • Motorola 68K-style 16-bit asynchronous interface
  • SRAM-like 16-bit asynchronous interface
  • PCI interface (33 MHz) compliant to PCI specification version 3.0 (supports PCI slave and master functions)
• DMA
  • Higher asynchronous throughput with DMA hardware enhancements (available in PCI mode only)
  • Internal DMA controller - Asynchronous, asynchronous Stream TX/RX
    • General DMA
    • Auto-response DMA for SBP2 transactions
• Data Buffers
  • Two 4-KByte isochronous buffers for video data
  • Two 2-KByte asynchronous/asynchronous stream transmit buffers
  • Two 2-KByte asynchronous/asynchronous stream receive buffers
  • One 1-KByte self-ID buffer
  • Insertion buffers for MPEG-DVB/DSS packet insertion
  • Programmable data/space available indicators for buffer flow control
• Hardware Packet Formatting for the Following Standards
  • IEC61883-1 (general)
  • IEC61883-2 (SD-DVCR)
  • IEC61883-4 (MPEG2-TS)
  • IEC61883-7 (ITU-R BO.1294 System B) - DSS
  • Generic 61883 mode
  • Asynchronous packets
  • Asynchronous streams
  • PHY packets (including self-IDs)
  • MPEG4 supported under IEC61883-4 (no new requirement for MPEG4 over 1394)
• Additional Features
  • JTAG interface to support post-assembly scan of device I/O - boundary scan
  • Unique "binding" method for protecting sensitive data on the circuit board traces at the Ex-CPU interface
  • Unique "EMI-AES Binding" method to prevent protected data from being transmitted in the clear.

Description

The TSB43Ex42/43 is high-performance consumer electronics 1394 link layer and integrated physical layer device designed for digitally interfacing advanced video consumer electronics applications. It supports formatting and transmission of IEC61883 data, including IEC61883-1 (general), IEC61883-2 (SD-DVCR), IEC61883-4 (MPEG2-TS), and IEC61883-7 (ITU-R BO.1294 SystemB-DSS). TSB43Ex42/43 also supports standard 1394 data types, such as asynchronous, asynchronous streams, and PHY packets.

The TSB43EAxx/ECxx version incorporates DTCP (M6) baseline per the DTLA (5C) specification to support transmit and receive of up to two MPEG2 transport streams with encryption and decryption. The TSB43EAxx/ECxx version also includes hardware acceleration for content key generation.

The TSB43EBxx devices are identical to the TSB43EAxx/ECxx devices, except without implementation of the encryption/decryption features. The TSB43EB42xx/43xx devices allow customers that do not require the encryption/decryption features to incorporate the TSB43Ex42/43 function without becoming DTLA licensees.

The TSB43Ex42/43 features an integrated 2-port/3-port PHY. The PHY operates at 100 Mbps, 200 Mbps, or 400 Mbps. They follow all requirements as stated in IEEE Std 1394-1995 and IEEE Std 1394a-2000.