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XIO1100 Status: ACTIVE

x1 PCI Express PHY

      
         
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Datasheet

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 XIO1100
Supply Voltage (Vcc)(Nom)(V)3.3 ,1.5 ,1.8  
PCIex1  
Parallel Bus Width8 ,16  
Speed(Max)(Gbps)2.5  
 Samples
 Inventory

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    • Product Information

    Features

    • X1 PCI Express™ Serial Link
      • PCI Express 1.1 Compliant
      • Selectable Reference Clock (100 MHz, 125 MHz)
      • Low-Power Capability
    • TI-PIPE MAC Interface
      • Source-Synchronous TX and RX Ports
      • 125 MHz TX/RX Clocks
      • Selectable 16-Bit SDR or 8-Bit DDR Mode
    • 100-Pin MicroStar™ BGA Package
    • Selectable 1.5-V or 1.8-V LVCMOS Buffers.

    TI and MicroStar BGA are trademarks of Texas Instruments Incorporated
    PCI Express is a trademark of PCI-SIG

    Description

    The XIO1100 is a PCI Express™ PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express™ Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.

    The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.

    • The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface with a 16-bit output bus (RXDATA) that is clocked by the RXCLK output clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are on the rising edge of the associated clock.
    • The 8-bit TI-PIPE interface is a 250 MHz 8-bit parallel interface with an 8-bit output bus (RXDATA) that is clocked by the RXCLK output clock and an 8-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Double Data Rate (DDR) clocking in which the data transitions are on both the rising edge and the falling edge of the clock.

    The XIO1100 PHY interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).

    The XIO1100 is also responsible for handling the 8B/10B encoding/decoding and scrambling/unscrambling of the outgoing data. In addition, XIO1100 can recover/interpolate the clock on the receiver side based on the transitions guaranteed by the use of the 8B/10B mechanism and supply this to the receive side of the data link layer logic.

    In addition to the TI-PIPE interface, the XIO1100 has some TI-proprietary side-band signals that some customers may wish to use to take advantage of additional XIO1100 low-power state features (for example, disabling the PLL during the L1 power state).

    		    

    Pricing / Packaging / CAD Design Tools / Samples

    PricePackagingCAD Design ToolsSamples
    DeviceStatusTemp (oC)Price | QuantityPackage | PinsPackage QTY | Package CarrierSymbolsFootprintsSamples
    XIO1100GGBACTIVE0 to 707.00 | 1kuBGA MICROSTAR (GGB) | 100 160 | JEDEC TRAY (5+1) Download CAD Format for this Symbol 
    XIO1100ZGBACTIVE0 to 707.00 | 1kuBGA (ZGB) | 100 160 | JEDEC TRAY (5+1) Download CAD Format for this Symbol Download CAD Format for this Footprint

    * Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For higher volume price quotes,prices in local currency or delivery quotes, please contact your local Texas Instruments Sales Office or Authorized Distributor.

    Inventory

      TI Inventory Status Reported Distributor Inventory
    XIO1100GGBAs of 7:59 AM GMT, 03 Jul 2009As of 7:59 AM GMT, 03 Jul 2009
     Lead TimeRegionCompanyIn StockPurchase
     4 Weeks AmericasAvnet 150
     DigiKey 975
     Mouser Electronics 15
     Rochester Electronics 355
     AsiaWPI 194
    XIO1100ZGBAs of 7:59 AM GMT, 03 Jul 2009As of 7:59 AM GMT, 03 Jul 2009
     Lead TimeRegionCompanyIn StockPurchase
     8 Weeks AmericasArrow 249
     DigiKey 43
     Mouser Electronics 154
     Rochester Electronics 138
     AsiaWPI 65
    View all Distributors  

    ** Lead time information is not available at this time. However, our information is updated daily so please check back with us soon. Please contact your preferred TI Authorized Distributor for additional information.

    Quality & Lead (Pb)-Free Data

     Product ContentDPPM / MTBF / FIT Rate
    DeviceEco Plan* Lead / Ball FinishMSL Rating / Peak ReflowDetailsDetails
    XIO1100GGB  TBD SNPB Level-3-220C-168 HRViewView
    XIO1100ZGB RoHS Compliant Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HRViewView

    * The planned eco-friendly classification: Pb-Free (RoHS) or Pb-Free (RoHS Exempt) or Green (RoHS & no Sb/Br) - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details.

    If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information.

    Technical Documents

    Most useful technical documents for XIO1100 Help

    Datasheet

    Application Notes

    Selection Guides

    Errata

    More Literature

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    Tools & Software

    NamePart # Company Tool / Software Type
    Spartan 3™/Cyclone II™ based x1 PCI Express Development kitSPARTAN-3TM-CYCLONE-IITM-PCI-EXPRESS-DEV-KITNorthwest LogicThird Party Development Environments

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