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CDCL6010EVM Evaluation Module Status: PREVIEW

CDCL6010EVM


      
         
Getting Started Documentation   CDCL6010EVM User's Guide (PDF 656 KB) 768 views
14 Mar 2007 

  CDCL6010EVM
NameCDCL6010EVM Evaluation Module
StatusPREVIEW
Price (US$) 
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Product Information

Description

The CDCL6010EVM is an evaluation module designed to aid in evaluating the performance of the CDCL6010, which is a 1:11 high-performance, low phase noise clock synthesizer that synchronizes its on-chip voltage controlled oscillator (VCO) frequency to an external reference clock; generates low phase noise (jitter) clock. The PLL loop bandwidth and damping factor can be modified by changing the on-board passive loop filter components to meet different system requirements. The input divider, feedback divider and output dividers are done through the programming interface. As the system requires external components like a microcontroller to aid in programming the device and a very clean power supply for the device, this EVM provides an excellent way to evaluate and modify the performance and parameters of the clock system in conjunction with the specific customer application.

Features

  • Output frequency from 15 MHz to 1.25 GHz
  • Loop bandwidth can be selected as low as 10 kHz to clean the system’s clock jitter
  • Can be used as a simple 1:11 LVDS/CML buffer with output dividing options
  • Differential outputs, input/feedback/output dividers programmable by I2C

What's Included

Order Options

 CDCL6010EVM
Name CDCL6010EVM Evaluation Module
Status  PREVIEW 
Price (US$)  
  
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