C6000 Embedded Design Workshop using SYS/BIOS
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Workshop Schedule and Pricing

United States $1595.00 Register Now

May 13-16, 2013 Dallas, TX


€1800 excluding VAT

For any further demand of this workshop in Europe, please submit your request here.

For any questions please contact asktexas@ti.com

Thank you - EMEA training organization.


The C6000 Embedded Design Workshop Using SYS/BIOS has been designed to use the latest hardware and software development tools available from Texas Instruments. In addition, this workshop builds around the concepts required to easily program simple DSP solutions and how to adapt them into increasingly more complex systems as system requirements evolve.

TI's SYS/BIOS RTOS supports multiple architectures: MSP430, Stellaris-M3, C28x, C6000 and other ARM platforms.

This workshop's primary focus is SYS/BIOS 6.3x running on a single-core DSP (C6748). However, the concepts discussed can be easily "ported" to ARM+DSP and multi-core devices (C66x) running SYS/BIOS or DSP/BIOS (BIOS ver 5.4x+). If users are primarily Linux/ARM focused, it might be a good idea to consider the 3-day Introduction to Embedded Linux 3-day Workshop Using AM335x available here.

The C6000 Embedded Design Workshop using SYS/BIOS is not intended to be platform specific. While the labs were written to run on OMAP-L138 EVM (C6748 AND OMAP-L138 SOMs) using CCS ver 5.2, the concepts and APIs apply to all TI C6000 platforms and can be helpful for users of CCSv3.3 or CCSv4 as well.

Although this workshop uses SYS/BIOS (a.k.a. BIOS 6.3x), the learning experience for DSP/BIOS users will be more than sufficient. API names change and there are some new features is SYS/BIOS, but what the O/S can do and how it works is relatively the same. Version 6.15+ has an optional chapter on DSP/BIOS (12a) that covers the most important topics related to creating DSP/BIOS projects using TCF files - and includes a lab. With increasing numbers of students wanting more info on SYS/BIOS, the decision was made to completely switch from DSP/BIOS to SYS/BIOS at this point.

The workshop is now broken into 4 new parts: "Core Essentials" (first 5 chapters), "Kicking It Up a Notch" (the next 3 chapters), "Advanced System Optimization" (chapters 9-12 - these really are ADVANCED) and "Grab Bag" (where we give students a choice of 3 topics to choose from). The goal here is that each person who attends this workshop should be very grounded in the first 5 chapters, the ESSENTIAL skills, after leaving the workshop. If students comprehend and are able to demonstrate skills in the "kicking it" and "advanced" chapters, that is even better. The "GrabBag" chapters can be covered as time and interest permits.

Almost every chapter has a lab - we really do believe in the fact that students learn more by DOING. Each of the first 10 chapters of the workshop include one or more hands-on lab sessions, intended to allow you to try out the concepts covered and increase your confidence to write code with the TI tools. Most of the labs adapt prior labs to new solutions, in the same manner as would be done in real life, rather than via fill in the blanks or other non-realistic simulations of actual DSP programming.

Choose the SYS/BIOS workshop if you are:

  • Developing code for the C6000 DSP using SYS/BIOS or DSP/BIOS
  • ARM + DSP user who wants to understand the DSP "black box" and the RTOS (BIOS) running on that CPU
  • MSP430, C28x, Stellaris-M3 user who wants a deeper dive into SYS/BIOS

ARM, Stellaris Cortex, MSP430, C55x, C28x Users:

  • ARM, Stellaris, MSP430 users will be using SYS/BIOS exclusively. You can learn a great deal about this RTOS in the SYS/BIOS workshop. The only architecture NOT supported by SYS/BIOS is C55x - but the RTOS concepts are the same between DSP and SYS/BIOS.

Choose the Introduction to Linux Workshop if you are:

  • primarily an ARM/Linux programmer

Most of the chapters in this workshop are NOW AVAILABLE online for all users. While we teach this workshop LIVE, the authors decided to record all chapters and labs for your benefit and access around the world. Voice-over PPTs are usually BORING. However, this training series is hosted by the two authors and offers lots of in-depth conversations about the tools and SYS/BIOS, highlighting, add'l info not included in the downloads, stories, panning/zooming, etc. to keep the users engaged and having a good time while learning SYS/BIOS and C6000 Architecture. The content also includes target-specific chapters on Stellaris and C6000. Don't wait...go check out this spectacular resource at your fingertips:

SYS/BIOS 1.5-day Workshop Videos

Course Author’s Official Wiki site:

Click“HERE” to go to the author’s official wiki site to read the most up-to-date info and contents for this workshop. The author posts all documentation (student guide and powerpoint slides) as well as all lab and solution files.

He also includes a lab environment setup guide that walks users through the entire setup process to create the lab environment based on the target platform – currently the OMAP-L138/C6748 EVM from LogicPD. So, for the latest info, go check out the author’s official wiki site…

Workshop Outline

Day 1

1. Devices

  • Provide an overview of the DSP, MCU, ARM and ARM+DSP devices from TI
  • Highlight a few of the peripherals on these devices
    • Lab 1: System Setup

2. Introduction to CCSv5

  • Describe the fundamentals of Code Composer Studio (CCS) v5
  • Demonstrate new features of CCSv5 such as workspaces, perspectives and views
  • Describe the device/system memory map and how to create a linker.cmd file
    • Lab 2: Create, build and debug several code examples using CCSv5

3. Introduction to SYS/BIOS

  • Explore the basic features of the SYS/BIOS Real-time Operating System (RTOS)
  • Define SYS/BIOS thread types and how the scheduler prioritizes threads in a system.
  • Learn how to create a new SYS/BIOS project
    • Lab 3: Creat, build and debug a SYS/BIOS application that blinks an LED

Day 2

4. C6000 Hardware Interrupts (Hwi)

  • Describe how a peripheral (McASP) works and how it generates an event (Hwi)
  • Describe how hardware interrupts (Hwi) work on a C64x +architecture
  • Demonstrate how to create an Hwi via CCS's config tool
    • Lab 4: Use an Hwi to respond to McASP interrupts

5. Using Threads - Swi and Tasks

  • Understand how Swi's complement Hwi's
  • Compare/contrast Swi and Tasks
  • Describe use of semaphores and Tasks in a system and how to create them
  • Identify how Tasks are prioritized within the BIOS scheduler
    • Lab 5: Use Swi to perform "ALGO" as follow-up to Hwi. Change Swi to Task.

6. Clock Functions and RTA Tools

  • Describe how to configure Clock Functions to execute periodically
  • Use Timestamp to benchmark code
  • Configure all the RTA tools - including Logs, Execution Graph and CPU/Thread Load
    • Lab 6: Add Clock Fxn and observe RTA results

7. Inter-thread Communication

  • Describe how to share resources between threads on a single-core DSP
  • Compare different use cases (concurrent access vs. producer/consumer model)
  • Analyze several BIOS building blocks for data sharing and signaling
  • Identify where semaphores can be a good choice vs. where they produce problems.

Day 3

8. Dynamic Memory (Heaps)

  • Compare/contrast static and dynamic systems
  • Define heaps and describe how to configure them
  • Describe how to eliminate the drawbacks of using std heaps (fragments,non-determinism)
  • Implement dynamic object creation
    • Lab 8: Create Semaphores and Tasks dynamically

9. C6000 Architecture

  • Provide a detailed overview of the C64x/C674x CPU architecture
  • Describe the basic ASM language and hardware needed to solve a SOP
  • Analyze how the hardware pipeline works
  • Learn basics of software pipelining

10. C and System Optimizations

  • Describe how to configure and use the various compiler/optimizer options
  • Discuss the key techniques to increase performance or reduce code size
  • Demonstrate how to use optimized libraries
  • Overview key system optimizations
    • Lab 10: Use FIR algo on audio data, optimize using the compiler, benchmark

Day 4

11. Cache and Internal Memory

  • Compare and contrast different uses of memory (internal, external, cache
  • Define cache terms and definitions
  • Describe C6000 cache architecture
  • Demonstrate how to configure and use cache optimally
    • Lab 11: modify an existing sytem to use cache - benchmark solutions

12. Using EDMA3

  • Understand the basic terminology related to EDMA3
  • Be able to describe how a transfer starts, how it is configured and what happens after the transfer completes
  • Understand how EDMA3 interrupts are generated
  • Be able to easily read EDMA3 documentation and have a great context to work from to program the EDMA3 in your application

13. List of "Grab Bag" Topics - the following topics will be taught provided time and interest (students vote) Each topic takes about 30-45 minutes plus any lab time if necessary

  • Intro to DSP/BIOS
  • Booting from Flash
  • Drivers - SIO/PSP/IOM

Course Prerequisites

Familiarity with C programming will be very helpful, as all the code used and written in the class is C based. Some experience with basic object oriented coding and operating system code that is "thread-based" is also helpful. If you have minimal or no C coding experience, this course may challenge you beyond your limits. However, some people have been known to simply import the solution files and walk through the lab steps - which is totally acceptable. This is an adult-learning environment, so it is up to the student to challenge themselves at a level that will provide the best learning experience for them as an individual.

Since this class does not presume a particular TI DSP/MCU platform, no prior experience with any particular DSP or MCU hardware is required. However, experience with embedded system programming (memory management skills) is helpful, but not required.

All European and USA Multi-day workshops are conducted in English

Course Details

  Classes begin at 8:30 a.m. and run through 5:30 p.m. each day. You can expect to finish class between 2:00pm -4:00pm on the final day. 

Cancellation Policy

  • European classes are subject to cancellation if minimum number of attendees is not met one week prior to the date of the workshop.  
  • US classes are subject to cancellation if minimum number of attendees is not met two weeks prior to  the date of the workshop.
  • In the event of short notice cancellation Texas Instruments is liable solely for the refund of workshop fees.

   Minimum = 5   Maximum = 12